at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 31

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

4.8
4.9
4.10
9621B–AT42–06/11
Report Detections for All Keys – 0x07
Report Error Flags for All Keys – 0x0B
Dump Setups Block – 0x0D
If the Matrix Scan counter is read once every 100 ms, for example, the host should find the
counter has increased by 10 counts from the value returned at each previous read and should
traverse one full count range (256 steps) when the host has read the counter 25 or 26 times. The
host should verify the counter is incrementing at the expected rate. If the counter advances
faster or slower than expected, there could be a fault with the QT1481 or the host, and the host
should adopt an appropriate strategy to meet the required safety standard.
Note:
Returns six bytes which indicate all keys which are in detection, if any, as a bit-field. Key 0
reports in bit 0 of byte 0, the first byte returned. Key 47 is reported in bit 7 of byte 5. See
Table 4-3 on page
A 16-bit CRC is appended to the response; this CRC folds in the command 0x07 itself initially.
Table 4-3.
Returns six bytes which show error flags as a bit-field for all keys plus two CRC bytes. Key 0
reports in bit 0 of byte 0, the first byte returned; key 47 is reported in bit 7 of byte 5. See
Table 4-3
This command reports an error flag for each enabled key if calibration has failed or if the key has
a reference below the LSL (see
A 16-bit CRC is appended to the response. This CRC folds in the command 0x0B itself initially.
This command causes the QT1481 to dump the entire internal Setups block back to the host.
In UART mode, if the transfer is not paced faster than 110 ms ±5 ms per byte the transfer is
aborted and the QT1481 times out. This could happen if the host were controlling DRDY. In SPI
mode, the entire command must be competed within 110 ms ±5 ms or the transfer could be
aborted.
During the transfer, sensing is halted. Sensing is resumed after the command has finished.
A 16-bit CRC is appended to the response; this CRC is the same as the Setups table CRC and
is sent LSByte first.
Returned
(Y line #)
Number
Byte
The STATUS pin becomes inactive on processing this command if it was made active by
a key touch (or release). See
Set-ups byte.
and
Table 5-5 on page
Bit Fields for Multiple Key Reporting and Key Numbering
0
1
2
3
4
5
31.
15
23
31
39
47
7
7
Section 5.18 on page
55.
14
22
30
38
46
6
6
Section 5.20 on page 49
13
21
29
37
45
5
5
Bit Number (X Line Number)
12
29
28
36
44
4
4
48).
11
19
27
35
43
3
3
for STS_TOUCH in the STS
AT42QT1481
10
18
26
34
42
2
2
17
25
33
41
1
1
9
16
24
32
40
0
0
8
31