at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 25

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

3.5
9621B–AT42–06/11
Debug Output Interface
Due to the asynchronous nature of UART timing, reception of a byte is considered complete
when the receiver detects the stop bit, which is typically some considerable time before the
transmitter actually terminates the stop bit. Depending on the baud rate, it is therefore possible
for the QT1481 to assert the DRDY pulse and start transmitting a response during the stop bit of
the command from the host.
If the host needs to slow the pace of the QT1481 return data, it can assert DRDY before
transmitting the stop bit of the command byte.
Null Bytes: Unlike SPI mode, there is no reason to send null bytes to the QT1481 in UART
mode. The QT1481 responds to commands with data when ready, subject to the DRDY line
being high.
UART Noise: In some designs it is necessary to run Tx and Rx over a lengthy distance. This
can introduce ringing, ground bounce, and other noise problems which can corrupt data. Simple
RC networks and slower data rates are helpful to resolve these issues. A CRC is appended to
responses in order to detect transmission errors to a high level of certainty.
UART Timing Parameters: UART timings are as shown in
timings for parameters U2 and U3 are dependent on the specific command. See
Figure 3-4.
The QT1481 includes a debug interface which may be used for observing many internal
operating variables, in real time, even while the part is actively communicating with a host over
either the SPI or UART serial interfaces. The Debug interface provides a useful aid during
product development (see
DRDY (handshake)
Rx (command from host)
Tx(response to host)
UART Timing
Floats high
Section B on page
*
U1
U2
U3
65).
U1: <=100 µs U2, U3: See text
*
Stop bit
Figure 3-4 on page
*
AT42QT1481
Floats high
U4
Section
U4: <=10 µs
25. Delay
3.5.
25