at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 30

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

Bits 5 – 0: A 6-bit unsigned value encoding the first or only key to be touched, in the range 0 –
47. This number is valid only if the value encoded in bits 7, 6 is non-zero, indicating a key is
touched.
The EN60730 counters (100 ms, Matrix Scan, Signal Fail) can be used by the host to check the
correct speed and operation of the QT1481. The host must check these values regularly to meet
the requirements of EN60730.
EN60730 requires that each component of a system be checked for correct operation. Where
correct speed of operation must be confirmed and the QT1481 has no way to perform such a
cross-check internally, counters are exposed through this command to enable independent
cross-checking by the host.
100 ms Counter:
This is an 8-bit unsigned counter that is incremented once every 100 ms, counting 256 steps
repeatedly from 0 to 255. When the counter has reached 255 it wraps back to 0 at the next
100 ms interval. The counter should take between 25 and 26 seconds (256 x 100 ms = 25.6s) to
count up from zero to 255 and wrap back to zero again. The host must read this counter
regularly and cross-check the counting rate against one of its own clock sources.
If the 100 ms counter is read once every second, for example, the host should find the counter
has increased by 10 counts from the value returned at each previous read and should traverse
one full count range (256 steps) when the host has read the counter 25 or 26 times. The host
should verify that the 100 ms counter is incrementing at the expected rate. If the counter
advances faster or slower than expected, there could be a fault with the QT1481 or the host, and
the host should adopt an appropriate strategy to meet the required safety standard.
Signal Fail Counter:
This is an 8-bit unsigned counter that is incremented each time a signal capture failure occurs.
Signal capture failure can occur where keys are enabled but do not physically exist. Only keys
that exist should be enabled; all other keys should be disabled.
Signal capture failure can also occur where heavy noise spikes corrupt the signal; Occasional
capture failure is to be expected and does not unduly affect the QT1481 performance. Regular
capture failure would extend the key response time.
The host must check this counter regularly. Tests should be made with a heavy noise source
during development to determine how the key response time is affect and determine a maximum
acceptable count rate for this counter.
Matrix Scan Counter:
This is an 8-bit counter that is incremented before the start of each matrix scan, or keyscan
cycle, counting 256 steps repeatedly from 0 to 255. When the counter has reached 255 it wraps
back to 0 at the start of the next keyscan cycle. The keyscan cycle time should be measured
with an oscilloscope during development.
The Matrix Scan count rate can be calculated directly from this. For example, if the keyscan
cycle time is measured as 10 ms, the counter counts 256 steps in 2560 ms (256 x 10 ms). The
host must read this counter regularly to check the matrix scan is operating at the expected rate.
AT42QT1481
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