at91sam9g45 ATMEL Corporation, at91sam9g45 Datasheet - Page 15

• Manufacturer Part Number: at91sam9g45
• Description: At91 Arm Thumb-based Microcontrollers
• Manufacturer: ATMEL Corporation

6. Processor and Architecture
6.1
6438CS–ATARM–13-Oct-09
ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
• Two Instruction Sets
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
• 32-KByte Data Cache, 32-KByte Instruction Cache
• Write Buffer
• Standard ARM v4 and v5 Memory Management Unit (MMU)
• Bus Interface Unit (BIU)
• TCM Interface
acceleration
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
– 16 embedded domains
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
– Separate Address and Data Buses for both the 32-bit instruction interface and the
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
each quarter of the page
system flexibility
32-bit data interface
(Words)
AT91SAM9G45
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