at91sam9g45 ATMEL Corporation, at91sam9g45 Datasheet - Page 18

• Manufacturer Part Number: at91sam9g45
• Description: At91 Arm Thumb-based Microcontrollers
• Manufacturer: ATMEL Corporation

6.3
18
Peripheral DMA Controller (PDC)
AT91SAM9G45
Table 6-4
the Remap status (RCBx bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and
the BMS state at reset.
Table 6-4.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 6-5.
Instance name
DBGU
USART3
USART2
USART1
USART0
AC97
SPI1
SPI0
SSC1
SSC0
TSDAC
DBGU
USART3
USART2
USART1
USART0
AC97
SPI1
SPI0
SSC1
SSC0
• Acting as one AHB Bus Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
• Next Pointer support, prevents strong real-time constraints on buffer management.
of the processor.
Base Address
0x0000 0000
Slave
summarizes the Slave Memory Mapping for each connected Master, depending on
Internal Memory Mapping
Peripheral DMA Controller
Channel T/R
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
Receive
Receive
Receive
Receive
Receive
Receive
Receive
Receive
Internal ROM
BMS = 1
RCBx = 0
EBI NCS0
BMS
Master
= 0
Internal SRAM
RCBx = 1
6438CS–ATARM–13-Oct-09