at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 156

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Product
Dependencies
Power
Management
Interrupt Sources
Watchdog
Overflow
Functional
Description
System Timer
Clock
Period Interval
Timer (PIT)
156
AT91RM3400
The System Timer is continuously clocked at 32768 Hz. The power management controller
has no effect on the system timer behavior.
The System Timer interrupt is generally connected to the source 1 of the Advanced Interrupt
Controller. This interrupt line is the result of the OR-wiring of the system peripheral interrupt
lines (System Timer, Real Time Clock, Power Management Controller, Memory Controller).
When a system interrupt happens, the service routine must first determine the cause of the
interrupt. This is accomplished by reading successively the status registers of the above men-
tioned system peripherals.
The System Timer is capable of driving the NWDOVF pin. This pin might be implemented or
not in a product. When it is implemented, this pin might or not be multiplexed on the PIO Con-
trollers even though it is recommended to dedicate a pin to the watchdog function. If the
NWDOVF is multiplexed on a PIO Controller, this last should be first programmed to assign
the pin to the watchdog function before using the pin as NWDOVF.
When it is not implemented, programming the associated bits and registers has no effect on
the behavior of the System Timer.
The System Timer uses only the SLCK clock so that it is capable to provide periodic, watch-
dog, second change or alarm interrupt even if the Power Management Controller is
programmed to put the product in Slow Clock Mode. If the product has the capability to back
up the Slow Clock oscillator and the System Timer, the System Timer can continue to operate.
The Period Interval Timer can be used to provide periodic interrupts for use by operating sys-
tems. The reset value of the PIT is 0 corresponding to the maximum value. It is built around a
16-bit down counter, which is preloaded by a value programmed in ST_PIMR (Period Interval
Mode Register). When the PIT counter reaches 0, the bit PITS is set in ST_SR (Status Regis-
ter), and an interrupt is generated if it is enabled.
The counter is then automatically reloaded and restarted. Writing to the ST_PIMR at any time
immediately reloads and restarts the down counter with the new programmed value.
Warning: If ST_PIMR is programmed with a period less or equal to the current MCK period,
the update of the PITS status bit and its associated interrupt generation are unpredictable.
Figure 49. Period Interval Timer
Slow Clock
SLCK
Down Counter
16-bit
PIV
PITS
1790A–ATARM–11/03