PF38F5070M0P0B NUMONYX [Numonyx B.V], PF38F5070M0P0B Datasheet - Page 18

• Manufacturer Part Number: PF38F5070M0P0B
• Description: Numonyx Wireless Flash Memory (W18)
• Manufacturer: NUMONYX [Numonyx B.V]

4.2
Table 7:
Datasheet
18
Symbol
D[15:0]
A[22:0]
ADV#
RST#
VCCQ
VSSQ
WAIT
WE#
WP#
CE#
OE#
VCC
VSS
CLK
VPP
DU
NC
Signal Descriptions - VF BGA Package
Output
Output
Input/
Power
Power
Power
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
Signal Descriptions
Table 7
signals used on the QUAD+ package.
—
—
ADDRESS INPUTS: For memory addresses. 32-Mbit: A[20:0]; 64-Mbit: A[21:0]; 128-Mbit: A[22:0]
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, protection register, and configuration code reads. Data pins float when the
chip or outputs are deselected. Data is internally latched during writes.
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous
read operations, all addresses are latched on ADV#’s rising edge or the next valid CLK edge with
ADV# low, whichever occurs first.
CHIP ENABLE: Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.
De-asserting CE# deselects the device, places it in standby mode, and places all outputs in High-Z.
CLOCK: CLK synchronizes the device to the system bus frequency during synchronous reads and
increments an internal address generator. During synchronous read operations, addresses are latched
on ADV#’s rising edge or the next valid CLK edge with ADV# low, whichever occurs first.
OUTPUT ENABLE: When asserted, OE# enables the device’s output data buffers during a read cycle.
When OE# is deasserted, data outputs are placed in a high-impedance state.
RESET: When low, RST# resets internal automation and inhibits write operations. This provides data
protection during power transitions. de-asserting RST# enables normal operation and places the
device in asynchronous read-array mode.
WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to
be asserted-high or asserted-low based on bit 10 of the Read Configuration Register. WAIT is tri-stated
if CE# is deasserted. WAIT is not gated by OE#.
WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the
rising edge of WE#.
WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down
mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See
Section 13.1, “Block Lock Operations” on page 71
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V
not be attempted.
Set V
from the system supply, the V
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin
at 12 V may reduce block cycling capability.
DEVICE POWER SUPPLY: Writes are inhibited at V
voltages should not be attempted.
OUTPUT POWER SUPPLY: Enables all outputs to be driven at V
VCC.
GROUND: Pins for all internal device circuitry must be connected to system ground.
OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied
directly to VSS.
DO NOT USE: Do not use this pin. This pin should not be connected to any power supplies, signals or
other pins and must be floated.
NO CONNECT: No internal connection; can be driven or floated.
PP2
describes the signals used on the VF BGA package.
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
PP
= V
CC
for in-system program and erase operations. To accommodate resistor or diode drops
IH
level of V
PP
≤ V
Name and Function
PPLK
PP
can be as low as V
. Block erase and program at invalid V
CC
≤ V
Numonyx™ Wireless Flash Memory (W18)
Numonyx™ Wireless Flash Memory (W18)
LKO
. Device operations at invalid V
PP1
CCQ
for details on block locking.
min. V
. This input may be tied directly to
Table 8
PP
must remain above V
Order Number: 290701-18
describes the
PP
voltages should
November 2007
CC
PP1