PF38F5070M0P0B NUMONYX [Numonyx B.V], PF38F5070M0P0B Datasheet - Page 79

• Manufacturer Part Number: PF38F5070M0P0B
• Description: Numonyx Wireless Flash Memory (W18)
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ Wireless Flash Memory (W18)
Table 31: Read Configuration Register Descriptions (Sheet 2 of 2)
14.1
14.2
Figure 36: First Access Latency Configuration
Note:
)
November 2007
Order Number: 290701-18
Notes:
1.
2.
3.
4.
5.
6.
Address [A]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
2-0
Bit
ADV# [V]
3
Other First Access Latency Configuration settings are reserved.
CLK [C]
Undocumented combinations of bits are reserved by Numonyx for future implementations.
Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status Register
and configuration reads support single read cycles. RCR[15]=1 disables configuration set by RCR[14:0].
Data is not ready when WAIT is asserted.
Set the synchronous burst length. In asynchronous page mode, the page size equals four words.
Set all reserved Read Configuration Register bits to zero.
Setting the Read Configuration Register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010),
data hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before delay (RCR[8] =1) is not supported.
Read Mode (RCR[15])
All partitions support two high-performance read configurations: synchronous burst
mode and asynchronous page mode (default). RCR[15] sets the read configuration to
one of these modes.
Status register, query, and identifier modes support only asynchronous and single-
synchronous read operations.
First Access Latency Count (RCR[13:11])
The First Access Latency Count (RCR[13:11]) configuration tells the device how many
clocks must elapse from ADV# de-assertion (V
driven onto its data pins. The input clock frequency determines this value. See
Table 31, “Read Configuration Register Descriptions” on page 78
Figure 36
to
Section , “” on page 80
Burst Length
Burst Wrap
Address
Valid
BL[2:0]
Name
BW
shows data output latency from ADV# assertion for different latencies. Refer
Code 3
Code 4
Code 5
Code 2
0 = Wrap bursts within burst length set by CR[2:0]
1 = Don’t wrap accesses within burst length set by CR[2:0].(Default)
001 = 4-Word Burst
010 = 8-Word Burst
011 = 16-Word Burst
111 = Continuous Burst (Default)
for Latency Code Settings.
Output
Valid
Output
Output
Valid
Valid
Description
IH
) before the first data word should be
Output
Output
Output
Valid
Valid
Valid
1
Output
Output
Output
Output
Valid
Valid
Valid
Valid
for latency values.
Output
Output
Output
Output
Valid
Valid
Valid
Valid
Output
Output
Output
Output
Datasheet
Valid
Valid
Valid
Valid
Notes
4
79