PF38F5070M0P0B NUMONYX [Numonyx B.V], PF38F5070M0P0B Datasheet - Page 55

• Manufacturer Part Number: PF38F5070M0P0B
• Description: Numonyx Wireless Flash Memory (W18)
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ Wireless Flash Memory (W18)
10.0
10.1
Note:
10.2
November 2007
Order Number: 290701-18
Read Operations
The device supports two read modes - asynchronous page and synchronous burst
mode. Asynchronous page mode is the default read mode after device power-up or a
reset. The Read Configuration Register (RCR) must be configured to enable
synchronous burst reads of the flash memory array (see
Configuration Register” on page
Each partition of the device can be in any of four read states: Read Array, Read
Identifier, Read Status or CFI Query. Upon power-up, or after a reset, all partitions of
the device default to the Read Array state. To change a partition’s read state, the
appropriate read command must be written to the device (see
Commands” on page
The following sections describe device read modes and read states in detail.
Asynchronous Page Read Mode
Following a device power-up or reset, asynchronous page mode is the default read
mode and all partitions are set to Read Array. However, to perform array reads after
any other device operation (e.g. write operation), the Read Array command must be
issued in order to read from the flash memory array.
Asynchronous page-mode reads can only be performed when Read Configuration
Register bit RCR[15] is set (see
page
To perform an asynchronous page mode read, an address is driven onto A[MAX:0], and
CE#, OE# and ADV# are asserted. WE# and RST# must be deasserted. WAIT is
asserted during asynchronous page mode. ADV# can be driven high to latch the
address, or it must be held low throughout the read cycle. CLK is not used for
asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be
performed, CLK should be tied to a valid V
ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial access
time t
In asynchronous page mode, four data words are “sensed” simultaneously from the flash
memory array and loaded into an internal page buffer. The buffer word corresponding
to the initial address on A[MAX:0] is driven onto DQ[15:0] after the initial access delay.
Address bits A[MAX:2] select the 4-word page. Address bits A[1:0] determine which
word of the 4-word page is output from the data buffer at any given time.
Synchronous Burst Read Mode
Read Configuration Register bits RCR[15:0] must be set before synchronous burst
operation can be performed. Synchronous burst mode can be performed for both array
and non-array reads such as Read ID, Read Status or Read Query (See for details).
Synchronous burst mode outputs 4, 8, 16, or . To perform a synchronous burst- read, an
initial address is driven onto A[MAX:0], and CE# and OE# are asserted. WE# and
RST# must be deasserted. ADV# is asserted, and then deasserted to latch the address.
Alternately, ADV# can remain asserted throughout the burst access, in which case the
address is latched on the next valid CLK edge after ADV# is asserted. See
“Set Read Configuration Register” on page 78
During synchronous array and non-array read modes, the first word is output from the
data buffer on the next valid CLK edge after the initial access latency delay (see
14.2, “First Access Latency Count (RCR[13:11])” on page
78).
AVQV
delay. (see
50).
Section 7.0, “AC Characteristics” on page
Section 14.0, “Set Read Configuration Register” on
78).
IH
level, WAIT signal can be floated and
Section 14.0, “Set Read
79). Subsequent data is
Section 9.2, “Device
26).
Section 14.0,
Section
Datasheet
55