PF38F5070M0P0B NUMONYX [Numonyx B.V], PF38F5070M0P0B Datasheet - Page 9

• Manufacturer Part Number: PF38F5070M0P0B
• Description: Numonyx Wireless Flash Memory (W18)
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ Wireless Flash Memory (W18)
2.0
November 2007
Order Number: 290701-18
Functional Overview
This section provides an overview of the W18 device features and architecture.
The W18 device provides Read-While-Write (RWW) and Read-White-Erase (RWE)
capability with high-performance synchronous and asynchronous reads on package-
compatible densities with a 16-bit data bus. Individually-erasable memory blocks are
optimally sized for code and data storage. Eight 4-Kword parameter blocks are located
in the parameter partition at either the top or bottom of the memory map. The rest of
the memory array is grouped into 32-Kword main blocks.
The memory architecture for the W18 device consists of multiple 4-Mbit partitions, the
exact number depending on device density. By dividing the memory array into
partitions, program or erase operations can take place simultaneously during read
operations. Burst reads can traverse partition boundaries, but user application code is
responsible for ensuring that they don’t extend into a partition that is actively
programming or erasing. Although each partition has burst-read, write, and erase
capabilities, simultaneous operation is limited to write or erase in one partition while
other partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of this
device. An erase can be suspended to perform a program or read operation within any
block, except that which is erase-suspended. A program operation nested within a
suspended erase can subsequently be suspended to read yet another memory location.
After device power-up or reset, the W18 device defaults to asynchronous page-mode
read configuration. Writing to the device’s Read Configuration Register (RCR) enables
synchronous burst-mode read operation. In synchronous mode, the CLK input
increments an internal burst address generator. CLK also synchronizes the flash
memory with the host CPU and outputs data on every, or on every other, valid CLK
cycle after an initial latency. A programmable WAIT output signals to the CPU when
data from the flash memory device is ready.
In addition to its improved architecture and interface, the W18 device incorporates
Enhanced Factory Programming (EFP), a feature that enables fast programming and
low-power designs. The EFP feature provides the fastest currently-available program
performance, which can increase a factory’s manufacturing throughput.
The device supports read operations at 1.8 V and erase and program operations at 1.8
V or 12 V. With the 1.8 V option, VCC and VPP can be tied together for a simple, ultra-
low-power design. In addition to voltage flexibility, the dedicated VPP input provides
complete data protection when V
This device (130 nm) allows I/O operation at voltages lower than the minimum V
1.7 V. This Extended V
flexibility.
A 128-bit protection register enhances the user’s ability to implement new security
techniques and data protection schemes. Unique flash device identification and fraud-,
cloning-, or content- protection schemes are possible through a combination of factory-
programmed and user-OTP data cells. Zero-latency locking/unlocking on any memory
block provides instant and complete protection for critical system code and data. An
additional block lock-down capability provides hardware protection where software
commands alone cannot change the block’s protection status.
The Command User Interface (CUI) is the system processor’s link to internal flash
memory operation. A valid command sequence written to the CUI initiates device Write
State Machine (WSM) operation that automatically executes the algorithms, timings,
CCQ
range, 1.35 V – 1.8 V, permits even greater system design
PP
≤ V
PPLK
.
Datasheet
CCQ
of
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