PF38F5070M0P0B NUMONYX [Numonyx B.V], PF38F5070M0P0B Datasheet - Page 49

• Manufacturer Part Number: PF38F5070M0P0B
• Description: Numonyx Wireless Flash Memory (W18)
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ Wireless Flash Memory (W18)
9.1.2
9.1.3
9.1.4
November 2007
Order Number: 290701-18
The appropriate CUI command must be written to the partition in order to place it in
the desired read state (see
Non-array read operations (Read ID, CFI Query, and Read Status Register) execute as
single synchronous or asynchronous read cycles. WAIT is asserted throughout non-
array read operations.
Writes
Device write operations are performed by placing the desired address on A[22:0] and
asserting CE# and WE#. OE# and RST# must be high. Data to be written at the
desired address is placed on DQ[15:0]. ADV# must be held low throughout the write
cycle or it can be toggled to latch the address. If ADV# is held low, the address and
data are latched on the rising edge of WE#. CLK is not used during write operations,
and is ignored; it can be either free-running or halted at V
are asynchronous.
Table 22, “Command Codes and Descriptions” on page 51
commands.
on moving between different device operations by using CUI commands.
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state.
Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous-
burst read operation. This can be useful if the system needs to access another device
on the same address and data bus as the flash during a burst-read operation.
Synchronous-burst accesses can be suspended during the initial latency (before data is
received) or after the device has output data. When a burst access is suspended,
internal array sensing continues and any previously latched internal data is retained.
Burst Suspend occurs when CE# is asserted, the current address has been latched
(either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK
can be halted when it is at V
and CLK is restarted. Subsequent CLK edges resume the burst sequence where it left
off.
Within the device, CE# gates WAIT. Therefore, during Burst Suspend WAIT is still
driven. This can cause contention with another device attempting to control the
system’s READY signal during a Burst Suspend. Systems using the Burst Suspend
feature should not connect the device’s WAIT signal directly to the system’s READY
signal. Refer to
• CFI Query: Returns Common Flash Interface (CFI) information. CFI information
• Read Status Register: Returns Status Register (SR) data from the addressed
can be accessed starting at 4-Mbit partition base addresses.
partition.
Appendix A, “Write State Machine States” on page 86
Figure 13, “Burst Suspend” on page
Table 22, “Command Codes and Descriptions” on page
IH
or V
IL
. To resume the burst access, OE# is reasserted
36.
IL
shows the available device
or V
IH
. All write operations
provides information
Datasheet
51).
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