PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 107

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-41. 64-bit Target Burst Read Transaction with a 64-bit Local Interface
CLK
10
1
2
3
4
5
6
7
8
9
Data 1 and 2
Data 3 and 4
Data 5 and 6
Turn around
Turn around
PCI Data
Address
Phase
Wait
Wait
Wait
Idle
The PCI master asserts framen and drives ad[31:0] and cben[3:0]. It requests a 64-bit
transaction by asserting req64n with framen.
The master tri-states ad[63:0] and drives the first byte enables (Byte Enable 1 and 2)
cben[7:0]. If the PCI master is ready to receive data, it asserts irdyn.The Core starts to
decode the address and command.
The target drives the lt_address_out to the back-end. The lt_64bit_trans signal is driven
high to signal the back-end that a 64-bit transaction has been requested.
If there is an address match, the Core drives the bar_hit signals to the Local Interface. The
back-end application can use the bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the PCI IP core asserts devseln and ack64n on clock
after bar_hit. If the back-end will be ready to put data out on the next cycle, it can assert
lt_rdyn. The Core acknowledges the 64-bit transaction by asserting ack64n.
The PCI IP core asserts lt_ldata_xfern and lt_hdata_xfern since lt_rdyn was asserted
the previous cycle. The back-end drives the first QWORD (Data 1 and 2) on l_ad_in.
With lt_rdyn asserted previous two cycles, the burst cycle starts, so the Core asserts trdyn
and puts (Data 1 and 2) on ad[63:0].If both irdyn and lt_rdyn are asserted on the previous
cycle, the Core keeps lt_ldata_xfern and lt_hdata_xfern asserted to the back-end. The
back-end can increment the address counter and put the next QWORD (Data 3 and 4) on
l_ad_in.
If the master is still ready to receive data, it keeps irdyn asserted and drives the next byte
enables (Byte Enable 3 and 4) on cben[7:0].If the back-end keeps lt_rdyn asserted previous
two cycles, the PCI IP core keeps trdyn asserted and puts (Data 3 and 4) on ad[63:0].
If both irdyn and lt_rdyn are asserted on the previous cycle, the Core keeps
lt_ldata_xfern and lt_hdata_xfern asserted. The back-end application can increment the
address counter and put the next QWORD (Data 5 and 6) on l_ad_in.
If the PCI master is still ready to receive data, it keeps irdyn asserted and drives the next byte
enables (Byte Enable 5 and 6) on cben[7:0].
The PCI master signals the end of the burst when it de-asserts framen and req64n.If the back-
end application keeps lt_rdyn asserted for the previous two cycles, the Core keeps trdyn
asserted and puts Data 5 and 6 on ad[63:0].
If both irdyn and lt_rdyn are asserted on the previous cycle, the Core keeps
lt_ldata_xfern and lt_hdata_xfern asserted. The back-end application can increment the
address counter and put the next QWORD (Don’t care) on l_ad_in.
The master relinquishes control of framen, req64n and cben[7:0]. It de-asserts irdyn if both
trdyn and irdyn were asserted last cycle.
The Core relinquishes control of ad[63:0]. It de-asserts devseln, ack64n and trdyn if both
trdyn and irdyn were asserted last cycle. The Core also signals to the back-end that the trans-
action is complete by clearing bar_hit. The target de-asserts lt_ldata_xfern and
lt_hdata_xfern.
The Core relinquishes control of devseln, ack64n and trdyn.
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Description
Functional Description
PCI IP Core User’s Guide