PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 75

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-26. 32-bit Master Dual Address Cycle – Write Transaction (Continued)
CLK
10
5
6
7
8
9
Address
Address
Phase
Data 1
Data 2
High
Wait
Low
Idle
If both lm_req32n and gntn were asserted on the previous cycle, lm_status[3:0] is changed
to ‘Address Loading’ to indicate the starting address, the bus command and the burst length are
being latched.
The Core asserts framen and the local master de-asserts lm_req32n when the previous
lm_status[3:0] was ‘Address Loading’ and if it doesn’t want to request another PCI bus trans-
action.
Since lm_status[3:0] was ‘Address Loading’ on the previous cycle, it also drives the PCI start-
ing address on ad[31:0] and the PCI command (DAC) on cben[3:0]. On the same cycle, it
keeps lm_status[3:0] as ‘Address Loading’ for the Dual Address Cycle.
Local master provides high 32-bit address on l_ad_in[31:0].
lm_burst_cnt gets the value of the burst length.
The Core de-asserts reqn when framen was asserted but lm_req32n was de-asserted on the
previous cycle.
The Core keeps framen to start transaction.
Since lm_status[3:0] was ‘Address Loading’ on the previous cycle, it also drives the PCI
higher starting address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle,
it outputs lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data
phases.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master should provide Data 1 on l_ad_in[31:0] and the byte enables on
lm_cben_in[3:0]. And the Core asserts lm_data_xfern to the local master to signify these
data and byte enables are being read and will be transferred to the PCI bus.
Asserting lm_rdyn means the local master is ready to write data. If it is not, it should keep
lm_rdyn de-asserted until it is ready.
The Core de-asserts reqn when framen was asserted.
lm_data_xfern is kept asserted to signify Data 2 on l_ad_in[31:0] and the byte enables on
lm_cben_in[3:0] are being read and will be transferred to the PCI bus.
If the local master is ready to provide the next DWORD, it keeps lm_rdyn asserted.
The Core keeps framen asserted and asserts irdyn. It also de-asserts lm_data_xfern to the
local master to signify Data 3 on l_ad_in[31:0] are not read.
If the local master is ready to provide the next DWORD, it keeps lm_rdyn asserted.
Because the Core performs the burst transactions, it keeps framen asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases lm_burst_cnt.
Since Data 1 on PCI bus were read by the target, the Core transfers Data 2 and their byte enables
to ad[31:0] and cben[3:0].
With lm_rdyn asserted previous cycle, the Core keeps irdyn asserted.
Because both lm_rdyn and trdyn were asserted on the previous cycle, the Core asserts
lm_data_xfern to signify Data 3 on l_ad_in[31:0] and the byte enables on
lm_cben_in[3:0] are being read and will be transferred to the PCI bus.
Because Data 3 are the last data, the local master de-asserts lm_rdyn.
Since both irdyn and trdyn are asserted, the second data phase is completed on this cycle.
75
Description
Functional Description
PCI IP Core User’s Guide