PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 70

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-24. 32-bit Master Burst Write Transaction With a 64-bit Local Interface (Continued)
Dual Address Cycle (DAC)
The PCI IP core application logic issues a Dual Address Cycle (DAC) command to inform the PCI IP core of its
usage of 64-bit addressing. In response, the Core executes two back-to-back address phases for the target. The
PCI IP core issues DAC to handle memory maps that are larger than the 4GB limitation of the 32-bit memory map.
64-bit addressing is not restricted to only 64-bit configurations of the PCI IP core.
Figure 2-21
description of the dual address cycle.
CLK
10
11
11
12
13
9
shows an example of the DAC during a 32-bit read transaction.
Turn around
Phase
Data 1
Data 2
Data 3
Data 4
Idle
Since lm_ldata_xfern and lm_hdata_xfern were not asserted on the previous cycle, the
local master keeps Data 3 and Data 4 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0].
With both devseln and lm_rdyn asserted previous cycle, the master asserts irdyn, and it pre-
pares for the 32-bit write burst.
The Core keeps framen asserted. It also keeps lm_ldata_xfern and lm_hdata_xfern de-
asserted to the local master to signify Data 3 and Data 4 on l_ad_in[63:0] are not read.
Because the Core performs the burst transactions, it keeps framen asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases ‘lm_burst_cnt’.
Since Data 1 on PCI bus were read by the target, the Core transfers Data 2 and their byte enables
to ad[31:0] and cben[3:0].
The Core keeps irdyn asserted.
Because trdyn were asserted on the previous cycle, the Core asserts lm_ldata_xfern and
de-asserts lm_hdata_xfern to the local master to signify Data 3 on l_ad_in[31:0] and the
byte enables on lm_cben_in[3:0] are being read and will be transferred to the PCI bus.
The Core keeps framen asserted to the target to signify the burst continues.
Since both irdyn and trdyn are asserted, the second data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases ‘lm_burst_cnt’.Since Data
2 on PCI bus was read, the Core transfers Data 3 and its byte enables to ad[31:0] and
cben[3:0].The Core keeps irdyn asserted. Because trdyn was asserted on the previous
cycle, the master de-asserts lm_ldata_xfern and asserts lm_hdata_xfern to the local mas-
ter to signify Data 4 on l_ad_in[63:32] and the byte enables on lm_cben_in[7:4] are
being read and will be transferred to the PCI bus. Since both irdyn and trdyn are asserted, the
third data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases ‘lm_burst_cnt’.
Since Data 3 on PCI bus were read, the Core transfers Data 4 and their byte enables to ad[31:0]
and cben[3:0].
The Core keeps irdyn asserted. Because the current transaction is the last, the Core de-asserts
framen and req64n to signal the end of the burst, also it de-asserts lm_ldata_xfern and
lm_hdata_xfern.
Since both irdyn and trdyn are asserted, the fourth data phase is completed on this cycle.
The Core relinquishes control of framen, req64n, ad and cben. It de-asserts irdyn, decreases
‘lm_burst_cnt’ to zero and changes lm_status[3:0] into ‘Bus Termination’ with
lm_termination as ‘Normal Termination’ because both trdyn and irdyn were asserted last
cycle.The target de-asserts devseln and trdyn.
The Core relinquishes control of irdyn, par and par64.
70
Description
Table 2-25
Functional Description
PCI IP Core User’s Guide
gives a clock-by-clock