PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 136

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Table 3-1. Parameter Descriptions
IPUG18_09.2, November 2010
The IPexpress tool is used to create IP and architectural modules in the Diamond and ispLEVER software. Refer to
“IP Core Generation” on page 143
Table 3-1
using the PCI IP core Configuration GUI in IPexpress. The numerous PCI Express parameter options are parti-
tioned across multiple GUI tabs as shown in this chapter.
Bus
PCI Data Bus Size
Local Master Data Bus Size
Local Target Data Bus Size
Local Data Bus Size
Local Address Bus Width
Bus Speed
Identification
Vendor ID [15:0]
Device ID [15:0]
Subsystem Vendor ID [15:0]
Subsystem ID [15:0]
Revision ID [7:0]
Class Code (Base Class, Sub
Class Interface)
Options
Timing of DEVSEL
Expansion ROM
Address Space Size
Capabilities Pointer [7:0]
CardBus CIS Pointer [31:0]
Fast Back to Back
Interrupt Acknowledge
Interrupt Pin
PCI Master
Read Only Latency Timer
MIN_GNT
MAX_LAT
BARs
Number of BARs
BAR0
BAR1
1
1
provides the list of user configurable parameters for the PCI IP core. The parameter settings are specified
1
Parameter
2
1
1
1
for a description on how to generate the IP.
{Yes, No} 0x 00-FF
Enable, Disable
33MHz, 66MHz
0x 0000-FFFF
0x 0000-FFFF
0x 0000-FFFF
0x 0000-FFFF
0x 00000000 -
0x 00000000 -
0x 00000000 -
0x FFFFFFFF
0x FFFFFFFF
0x FFFFFFFF
None, 2k, 4k,
None, INTAN
8k, ... , 16M
0x 00-FF
0x 00-FF
0x 00-FF
0x 00-FF
0x 00-FF
0x 00-FF
Yes, No
Yes, No
Yes, No
Range
32, 64
32, 64
32, 64
32, 64
32, 64
slow
0 - 6
136
Parameter Settings
0x FFFFFFFD
0x FFFFFFF0
0x 00000000
Yes 0x 40
0x 0000
0x 1573
0x 0000
0x 0000
Default
PCI IP Core User’s Guide
Enable
INTAN
0x 01
0x 05
0x 00
0x 00
0x 00
0x 00
None
slow
Yes
No
No
32
32
32
32
32
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Chapter 3: