PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 21

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 2-6. Status Register Descriptions
IPUG18_09.2, November 2010
Status Register
The Status Register is a 16-bit read/write register that provides information on the capabilities of the PCI IP core. It
also reports the error status of the PCI IP core. The Status Register is located at the upper 16 bits of register loca-
tion 04h. Writes to the Status Register from the PCI bus are slightly different, given that bits can be reset but not
set. Writing a 1 to a bit in the status register resets it, but only if the current value of the bit is a 1. Writing a 0 to a bit
has no effect.
Figure 2-4. Status Register
Location
9-10
Bit
11
12
4
5
7
8
Detected Parity
Signaled System Error with serrn
Received Master Abort
Received Target Abort
Signaled Target Abort
devseln Timing
Master Data Parity Error
Fast Back-toBack Capable
66 MHz Capable
Capabilities List
Capabilities List is a read-only bit that indicates whether or not the device contains an address pointer to the start
of the Capabilities list. The bit is set to a 1 to indicate that the Capabilities Pointer at location 34h is valid. After
reset the value is set to a 0. The CAP_PTR_ENA parameter initializes this bit.
66MHz Capable is a read-only bit that is used to indicate that the device is capable of running at 66MHz. The bit is
set to a 1 if the device is 66MHz capable. The PCI_66MHZ_CAP parameter initializes this bit.
Fast Back-to-Back Capable is a read-only bit that indicates if the device is capable of handling fast back-to-back
transactions. The bit is set to a 1 if the device can accept these transactions. The FAST_B2B_CAP parameter ini-
tializes this bit.
Master Data Parity Error indicates that the bus master has detected a parity error during a transaction. A value of
1 means a parity error has occurred. After rest the bit is set to 0.
DEVSEL Timing bits indicate the slowest time for a device to assert the devseln signal for all accesses except the
configuration accesses. The PCI IP core only supports the slow decode setting. The DEVSEL_TIMING parameter
(bits 2 and 1) determines the DEVSEL timing.
00 - Fast (not supported)
01- Medium (not supported)
10 - Slow
11 - Reserved
Signaled Target Abort is set when the target terminates the cycle with a Target-Abort. Writing a 1 clears the Sig-
naled Target Abort.
Received Target Abort is set to a 1 by the Core after it terminates a cycle with a target abort.
Figure 2-4
and
Table 2-6
describe the Status Register that is implemented in the PCI IP core.
15
14
13
12
11
21
Description
10
9
8
7
6
5
Functional Description
4
PCI IP Core User’s Guide
3
0