PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 131

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-54. 32-bit Target Retry for Read Transaction
CLK
4
5
6
7
8
9
The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn
signal remains high to indicate that the back-end application is not ready to provide data. Because the target can
not complete any PCI data phases, the lt_rdyn signal remains high and the lt_disconnectn signal is driven
low.
The lt_data_xfern signal remains high because the lt_rdyn signal was high during the previous cycle.
The stopn signal is driven low on the PCI bus as the lt_disconnectn signal was driven low for the previous
two clock cycles.
The PCI master de-asserts the framen to acknowledge the retry initiated by the target.
The PCI master terminates the transaction by de-asserting the irdyn. The PCI IP core de-asserts the devseln
and stopn.
Idle
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Description
Functional Description
PCI IP Core User’s Guide