PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 117

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Fast Back-to-Back Transactions
The PCI IP core, as a target, can respond to a fast back-to-back transaction if a PCI master wants to perform two or
more consecutive transactions to the PCI IP core. The fast back-to-back transaction consists of two or more com-
plete PCI transactions without an idle state between them.
write transaction. The figure illustrates how the PCI interface correlates to the Local Interface. The table explains
each event in the figure with a clock-by-clock description.
Table 2-45. 32-Bit Target Dual Address Cycle
CLK
10
11
1
2
3
4
5
6
7
8
9
Turn around
Turn around
PCI Data
Address
Address
Phase
Data 1
Data 2
Data3
Wait
Wait
Wait
Idle
The master asserts framen and drives ad[31:0](lower address and cben[3:0](DAC).
The master drives the ad[31:0](higher address) and cben[3:0] (Bus command).
The master tri-states ad[31:0] and drives the first byte enables (Byte Enable 1) on cben[3:0].
If the master is ready to receive data, it asserts irdyn.
The Core starts to decode the address and command. The Core drives the lt_address_out to
the back-end application.
If there is an address match, the Core drives the bar_hit signals to the back-end. The back-end
can use bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on the clock after bar_hit. If
the back-end will be ready to put data out on the next cycle, it asserts lt_rdyn.
The Core asserts lt_data_xfern since lt_rdyn was asserted on the previous cycle. The
back-end drives the first DWORD (Data 1) on l_ad_in.
With lt_rdyn asserted previous two cycles, the PCI IP core asserts trdyn and puts Data 1 on
ad[31:0].
The Core asserts lt_data_xfern since lt_rdyn was asserted on the previous cycle. The
back-end drives the second DWORD (Data 2) on l_ad_in.
With lt_rdyn asserted previous two cycles, the PCI IP core asserts trdyn and puts Data 1 on
ad[31:0].
The Core asserts lt_data_xfern since lt_rdyn was asserted on the previous cycle. The
back-end drives the second DWORD (Data 3) on l_ad_in.
The master asserts irdyn and de-asserts framen.
With lt_rdyn asserted previous two cycles, the PCI IP core asserts trdyn and puts Data 3 on
ad[31:0].
The master relinquishes control of framen and cben[3:0]. It de-asserts irdyn if both trdyn
and irdyn were asserted last cycle.
The Core relinquishes control of ad. It de-asserts both devseln and trdyn if both trdyn and
irdyn were asserted last cycle. The Core also signals to the back-end that the transaction is
complete by clearing bar_hit. The Core de-asserts lt_data_xfern.
The Core relinquishes devseln and trdyn.
117
Figure 2-41
Description
and
Table 2-46
Functional Description
illustrate a fast back-to-back
PCI IP Core User’s Guide