PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 12

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
commands specified in the PCI Local Bus Specification, Revision 3.0.
mands.
Table 2-1. PCI IP Core Command Support
The PCI Master control supports data transfer requirements for both high and low throughput back-end applica-
tions. It maintains up to the maximum 528 MBytes per second (MBps) burst data transfer rate when operating at
66MHz with a 64-bit data bus. The Advanced Master Transactions section of this document describes burst data
transfers in further detail. For slower applications, single data phase transactions can also be easily implemented.
The Basic PCI Master Read and Write Transactions section describes these basic transactions in detail.
PCI Target Control
The PCI Target control interfaces with the PCI bus. It processes the address, data, command and control signals to
transfer data to and from the PCI IP core for both 32-bit and 64-bit PCI applications. A list of the supported PCI sig-
nals is available in the PCI Interface Signals section. Once the PCI Target control detects a transaction, it passes
the transaction information to the Local Interface control using the internal bus. It also responds to most Configura-
tion Space accesses with no intervention from the Local Interface. The PCI IP core supports all of the commands
specified in the PCI Local Bus Specification, Revision 3.0.
When designing for a particular target application, the back-end target design may not support all the commands
listed in
back-end target application does not support all the commands, it must issue the proper termination as described
in the Target Termination section of this document.
The PCI Target control supports the data transfer requirements for both high and low throughput back-end applica-
tions. It can maintain a 528 MBps transfer rate during burst transactions when operating at 66MHz with a 64-bit
data bus. The Advanced Target Transactions section describes the Burst transactions in further detail. For slower
applications, single data phase transactions can also be easily implemented. The Basic PCI Target Read and Write
Transactions section describes the these basic transactions in detail
Local Master Interface Control
The Local Master Interface facilitates master transactions on the PCI Bus with the commands listed in
The Local Master Interface Control passes the local master transaction request from the user’s application to the
PCI Master Control which then executes the PCI bus transaction.
Table
2-1. As a result, the PCI IP core does not transfer data using those commands. For cases where the
cben[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
Command
12
Table 2-1
lists the supported PCI commands.
Support
Ignored
Ignored
Ignored
Ignored
Table 2-1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
lists the supported PCI com-
Functional Description
PCI IP Core User’s Guide
Table
2-1.