PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 73

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-25. 32- Bit Dual Address Cycle – Read Transaction (Continued)
Figure 2-22
description of the dual address cycle.
CLK
11
11
12
shows an example of the DAC during a 32-bit write transaction.
Turn around
Phase
Data 3
Idle
Since the previous data phase was completed, the Core transfers Data2 on l_data_out[31:0]
and decreases the lm_burst_cnt.
If both trdyn and lm_rdyn were asserted on the previous cycle, the master asserts
lm_data_xfern to the local master to signify Data 2 are available on l_data_out[31:0]. With
lm_data_xfern asserted, the local master can safely read Data 2 and increment the address
counter.
With lm_rdyn asserted on the previous cycle, the Core keeps irdyn asserted.
Because the current transaction is the last, the Core de-asserts framen to signal the end of the
burst.
If the target is still ready to provide data, it keeps trdyn asserted and drives the next DWORD
(Data 3) on ad[31:0].
If the local master is ready to read the next DWORD, it keeps lm_rdyn asserted.
Since both irdyn and trdyn are asserted, the third data phase is completed in this cycle.
Since the previous data phase was completed, the Core transfers Data 3 on l_data_out[31:0]
and decreases the lm_burst_cnt to zero.
The Core relinquishes control of framen and cben. It de-asserts irdyn and changes
lm_status[3:0] into ‘Bus Termination’ with lm_termination as ‘Normal Termination’
because both trdyn and irdyn were asserted during the last cycle.
The target relinquishes control of ad[31:0]. It de-asserts devseln and trdyn.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_data_xfern to the local master to signify Data 3 are available on l_data_out[31:0]. With
lm_data_xfern asserted, the local master can safely read Data 3.
The Core relinquishes control of irdyn and de-asserts lm_data_xfern, and the local master
de-asserts lm_rdyn since all of the burst data have been read.
73
Description
Table 2-26
Functional Description
PCI IP Core User’s Guide
gives a clock-by-clock