PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 3

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Chapter 3. Parameter Settings .......................................................................................................... 136
Chapter 4. IP Core Generation........................................................................................................... 143
IPUG18_09.2, November 2010
Advanced Target Transactions ........................................................................................................................... 97
Target Termination............................................................................................................................................ 123
Bus Tab............................................................................................................................................................. 137
Identification Tab............................................................................................................................................... 139
Options Tab....................................................................................................................................................... 140
PCI Master Tab (PCI Master/Target Cores Only) ............................................................................................. 141
BARs Tab.......................................................................................................................................................... 141
BAR Configuration Options ............................................................................................................................... 142
Licensing the IP Core........................................................................................................................................ 143
Getting Started .................................................................................................................................................. 143
IPexpress-Created Files and Top Level Directory Structure............................................................................. 146
Instantiating the Core ........................................................................................................................................ 147
Running Functional Simulation ......................................................................................................................... 147
Synthesizing and Implementing the Core in a Top-Level Design ..................................................................... 148
Hardware Evaluation......................................................................................................................................... 148
Updating/Regenerating the IP Core .................................................................................................................. 149
32-bit PCI Target with a 32-bit Local Bus Memory Transactions ............................................................... 82
64-Bit PCI Target with a 64-Bit Local Bus.................................................................................................. 87
32-Bit PCI Target with a 64-Bit Local Bus.................................................................................................. 90
Configuration Read and Write Transactions .............................................................................................. 94
PCI Target I/O Read and Write Transactions ............................................................................................ 96
Wait States................................................................................................................................................. 97
Burst Read and Write Target Transactions.............................................................................................. 100
Dual Address Cycle (DAC)....................................................................................................................... 115
Fast Back-to-Back Transactions .............................................................................................................. 117
Advanced Configuration Accesses .......................................................................................................... 120
Disconnect With Data............................................................................................................................... 124
Disconnect Without Data.......................................................................................................................... 127
Retry......................................................................................................................................................... 130
Target Abort ............................................................................................................................................. 133
Bus Definition ........................................................................................................................................... 137
Backend Configuration............................................................................................................................. 138
Synthesis/Simulation Tools Selection ...................................................................................................... 138
Vendor ID [15:0] ....................................................................................................................................... 139
Device ID [15:0]........................................................................................................................................ 139
Subsystem Vendor ID [15:0] .................................................................................................................... 139
Subsystem ID [15:0]................................................................................................................................. 139
Revision ID [15:0]..................................................................................................................................... 139
Class Code (Base Class, Bus Class, Interface)....................................................................................... 139
Devsel Timing .......................................................................................................................................... 140
Expansion ROM BAR............................................................................................................................... 140
Interrupts .................................................................................................................................................. 141
Read Only Latency Timer ........................................................................................................................ 141
MIN_GNT ................................................................................................................................................. 141
MAX_LAT................................................................................................................................................. 141
Base Address Registers........................................................................................................................... 142
BAR Width................................................................................................................................................ 142
BAR Type................................................................................................................................................. 142
Address Space Size................................................................................................................................. 142
Prefetching Enable................................................................................................................................... 142
Enabling Hardware Evaluation in Diamond.............................................................................................. 148
Enabling Hardware Evaluation in ispLEVER............................................................................................ 149
3
PCI IP Core User’s Guide
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