PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 110

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
If the starting address is QWORD aligned, the first DWORD is assumed to be the lower DWORD of a QWORD.
Otherwise, it is the upper DWORD. If the starting address is not QWORD aligned, it must be DWORD aligned.
Figure 2-38
figure illustrates how the PCI interface correlates to the Local Interface. The table gives a clock-by-clock description
of each event in the figure.
Figure 2-38. 32-bit Target Burst Read Transaction with a 64-bit Local Interface
lt_command_out[3:0]
lt_cben_out[3:0]
lt_cben_out[7:4]
lt_64bit_transn
lt_address_out
lt_hdata_xfern
l_ad_in[63:32]
lt_ldata_xfern
l_ad_in[31:0]
bar_hit[5:0]
lt_access
cben[3:0]
and
ad[31:0]
devseln
framen
lt_r_nw
lt_rdyn
irdyn
trdyn
par
clk
Table 2-43
1
Don't care
Don't care
Command
Address
Bus
Don't care
Don't care
0x00
illustrate a burst transaction to a 32-bit PCI IP core with a 64-bit Local Interface. The
2
Address
Parity
Don't care
Don't care
3
4
Don't care
5
110
Byte Enable 1
Don't care
Data 1
6
Data 2
Bus Command
Byte Enable 1
Byte Enable 1
Don't care
Address
Data 1
0x01
7
Parity 1
Data 2
Data 3
Data
8
Parity 2
Data 3
Functional Description
Data
Don't care
9
PCI IP Core User’s Guide
Don't care
Parity 3
Data
10
Don't care
Don't care
0x00
11