PCI-MT32-XP-N2 Lattice, PCI-MT32-XP-N2 Datasheet - Page 29

• Manufacturer Part Number: PCI-MT32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 2-10. Customer Specific Parameters (Continued)
IPUG18_09.2, November 2010
1. When using the second method to configure parameters, only the second column is used.
2. When a BAR is not used, its corresponding core configuration signal bar_p should be 32’h0000_0002. To achieve this:
Notes to the list above:
a. Only I/O BAR has 8-byte or 4-byte size.
b. For the value of “x” – please refer to the definition of Bit[3:0] as shown in the Memory BAR Configuration section of this document.
c. Not all BARs can be set for 2Gbytes. The total BAR space in one system should not be more than 4Gbytes for a 32-bit address.
Configuration
In this case:
The default values shown are the read back value (using PCI read command) of the enabled BAR after all 1’s are written into that BAR (using
PCI write command).
Bar Configuration Details
Memory Type:
Bit[0]
Bit[2:1]
Bit[3]
Bit[31:4]
I/O Type:
Bit[0]
Bit[1]
Bit[31:2]
Bit[31:4/2] – memory or I/O size:
2Gbyte
1Gbyte
512Mbyte
256Mbyte
128Mbyte
64Mbyte
32Mbyte
16Mbyte
8Mbyte
4Mbyte
2Mbyte
1Mbyte
512kbyte
256Kbyte
128Kbyte
64Kbyte
32Kbyte
16Kbyte
8Kbyte
4Kbyte
2Kbyte
1Kbyte
512byte
256byte
128byte
64byte
32byte
16byte
8byte
4byte
unused
Port Inputs
• BARx_g value in PCI_params.v should be 0x0000_0000.
• The file para_cfg.v will translate value 0x0000_0000 to 0x0000_0002.
• Content of that BAR register in PCI Configuration Space is 0x0000_0000
Space
BAR type = 0 (memory space indicator)
Base address type:
Prefetch 1= enable, 0=disable (This bit indicates whether or not the BAR can prefetch data from memory)
Memory size
BAR type = 1 (I/O space indicator)
0 – Reserved
Memory size
00 – Located in 32-bit address space
01 – Reserved
10 – Located in 64-bit address space
11 – Reserved
Corresponding Parameter
Name in PCI_params.v
32'h8000_000_x
32'hC000_000_x
32'hE000_000_x
32'hF000_000_x
32'hF800_000_x
32'hFC00_000_x
32'hFE00_000_x
32'hFF00_000_x
32'hFF80_000_x
32'hFFC0_000_x
32'hFFE0_000_x
32'hFFF0_000_x
32'hFFF8_000_x
32'hFFFC_000_x
32'hFFFE_000_x
32'hFFFF_000_x
32'hFFFF_800_x
32'hFFFF_C00_x
32'hFFFF_E00_x
32'hFFFF_F00_x
32'hFFFF_F80_x
32'hFFFF_FC0_x
32'hFFFF_FE0_x
32'hFFFF_FF0_x
32'hFFFF_FF8_x
32'hFFFF_FFC_x
32'hFFFF_FFE_x
32'hFFFF_FFF_x
32'hFFFF_FFF_9
32'hFFFF_FFF_D
32'h0000_000_2
Range
29
Default
Functional Description
Description
PCI IP Core User’s Guide