ADT7475ARQZ ON Semiconductor, ADT7475ARQZ Datasheet - Page 10

• Manufacturer Part Number: ADT7475ARQZ
• Description: IC REMOTE THERMAL CTRLR 16-QSOP
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of ADT7475ARQZ

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Full Temp Accuracy: +/- 0.5 C
• Digital Output - Bus Interface: Serial (3-Wire, 4-Wire)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

without first writing to the address pointer register if the
address pointer register is already at the correct value.
However, it is not possible to write data to a register without
writing to the address pointer register because the first data
byte of a write is always written to the address pointer
register.
protocols, the ADT7475 also supports the read byte protocol
(for more information, see System Management Bus
Specifications Rev. 2.0, available from Intel).
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
Write Operations
different types of read and write operations. The ones used
in the ADT7475 are discussed in this section. The following
abbreviations are used in the diagrams:
S—Start
P—Stop
R—Read
W—Write
A—Acknowledge
A—No acknowledge
The ADT7475 uses the following SMBus write protocols.
Send Byte
command byte to a slave device as follows:
a register address to RAM for a subsequent single−byte read
from the same address. This operation is shown in Figure 16.
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry
out a single−byte read without asserting an intermediate stop
condition.
It is possible to read a data byte from a data register
In addition to supporting the send byte and receive byte
If several read or write operations must be performed in
The SMBus specification defines several protocols for
In this operation, the master device sends a single
For the ADT7475, the send byte protocol is used to write
If the master is required to read data from the register
1. The master device asserts a start condition on
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and
Figure 16. Setting a Register Address for
SDA.
by the write bit (low).
the transaction ends.
S
1
ADDRESS
SLAVE
Subsequent Read
2
W A
3
REGISTER
ADDRESS
4
A P
5 6
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10
Write Byte
and one data byte to the slave device as follows:
Read Operations
Receive Byte
register. The register address must be set up previously. In
this operation, the master device receives a single byte from
a slave device as follows:
a single byte of data from a register whose address has
previously been set by a send byte or write byte operation.
This operation is shown in Figure 18.
Alert Response Address
devices that allows an interrupting device to identify itself
to the host when multiple devices exist on the same bus.
output or an SMBALERT. One or more outputs can be
In this operation, the master device sends a command byte
The byte write operation is shown in Figure 17.
The ADT7475 uses the following SMBus read protocols.
This operation is useful when repeatedly reading a single
In the ADT7475, the receive byte protocol is used to read
Alert response address (ARA) is a feature of SMBus
The SMBALERT output can be used as either an interrupt
1. The master device asserts a start condition on
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA and
1. The master device asserts a start condition on
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA, and
Figure 18. Single−Byte Read from a Register
Figure 17. Single−Byte Write to a Register
SDA.
by the write bit (low).
the transaction ends.
SDA.
by the read bit (high).
the transaction ends.
S
1
ADDRESS W A
SLAVE
2
1
S
ADDRESS
SLAVE
2
3
REGISTER
ADDRESS
R
3
A
4
DATA
4
5
A
A P
DATA
5 6
6
A P
7 8