ADT7475ARQZ ON Semiconductor, ADT7475ARQZ Datasheet - Page 18

• Manufacturer Part Number: ADT7475ARQZ
• Description: IC REMOTE THERMAL CTRLR 16-QSOP
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of ADT7475ARQZ

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Full Temp Accuracy: +/- 0.5 C
• Digital Output - Bus Interface: Serial (3-Wire, 4-Wire)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 3 (FAN2) = 1, indicates that Fan 2 has dropped below
minimum speed.
Bit 2 (FAN1) = 1, indicates that Fan 1 has dropped below
minimum speed.
Bit 1 (OVT) = 1, indicates that a THERM overtemperature
limit has been exceeded.
SMBALERT Interrupt Behavior
interrupt can be generated for out−of−limit conditions. Note
how the SMBALERT output and status bits behave when
writing interrupt handler software.
status bits behave. Once a limit is exceeded, the
corresponding status bit is set to 1. The status bit remains set
until the error condition subsides and the status register is
read. The status bits are referred to as sticky because they
remain set until read by software. This ensures that an
out−of−limit event cannot be missed if software is polling
the device periodically. Note that the SMBALERT output
remains low for the entire duration that a reading is
out−of−limit and until the interrupt status register has been
read. This has implications for how software handles the
interrupt.
Handling SMBALERT Interrupts
interrupts, it is recommended to handle the SMBALERT
interrupt as follows:
The ADT7475 can be polled for status, or an SMBALERT
HIGH LIMIT
TEMPERATURE
STATUS BIT
Figure 24 shows how the SMBALERT output and sticky
To prevent the system from being tied up servicing
SMBALERT
STICKY
Figure 24. SMBALERT and Status Bit Behavior
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
4. Mask the interrupt source by setting the
5. Take the appropriate action for a given interrupt
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the
source.
appropriate mask bit in the interrupt mask registers
(0x74 and 0x75).
source.
interrupt status bit has cleared, reset the
corresponding interrupt mask bit to 0. This causes
the SMBALERT output and status bits to behave
as shown in Figure 25.
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
(TEMP BELOW LIMIT)
CLEARED ON READ
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Masking Interrupt Sources
Register 2 (0x75) allow individual interrupt sources to be
masked out to prevent SMBALERT interrupts. Note that
masking an interrupt source prevents only the SMBALERT
output from being asserted; the appropriate status bit is set
normally.
Interrupt Mask Register 1 (0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Interrupt Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2
Temperature.
Bit 5 (LT) = 1, masks SMBALERT for Local Temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1
Temperature.
Bit 2 (V
Bit 0 (V
Interrupt Mask Register 2 (0x75)
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (F4P) = 1, masks SMBALERT for Fan 4 failure.
If the TACH4 pin is being used as the THERM input, this bit
masks SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM limits).
Enabling the SMBALERT Interrupt Output
default. Pin 5 or Pin 9 can be reconfigured as an
SMBALERT output to signal out−of−limit conditions.
HIGH LIMIT
TEMPERATURE
STATUS BIT
SMBALERT
Figure 25. How Masking the Interrupt Source Affects
Interrupt Mask Register 1 (0x74) and Interrupt Mask
The SMBALERT interrupt function is disabled by
STICKY
CC
CCP
) = 1, masks SMBALERT for V
) = 1, masks SMBALERT for V
SMBALERT Output
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT CLEARED
(TEMP BELOW LIMIT)
CLEARED ON READ
(SMBALERT RE−ARMED)
CC
CCP
Channel.
Channel.