ISL6567CRZ Intersil, ISL6567CRZ Datasheet - Page 18

• Manufacturer Part Number: ISL6567CRZ
• Description: IC CTLR PWM 2PHASE BUCK 24-QFN
• Manufacturer: Intersil

Specifications of ISL6567CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66%
• Voltage - Supply: 4.9 V ~ 5.5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-VQFN
• Frequency-max: 1.5MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 20 details the normalized maximum power dissipation
R
graph provided, find the power dissipation level
corresponding to the minimum input voltage and the input
voltage range and multiply it by the maximum desired bias
current to obtain the maximum power R
Alternately, the maximum power dissipation inside R
can be calculated using Equation 13.
P
Maximum power dissipation in the bias resistor will take
place at the upper end of the input voltage range. Select a
resistor with a power dissipation rating above the calculated
value and pay attention to design aspects related to the
FIGURE 20. NORMALIZED RESISTOR POWER DISSIPATION
MAXRBIAS
FIGURE 19. NORMALIZED RESISTOR VALUE IN PASSIVE
BIAS
150
135
120
105
90
75
60
45
30
15
6
5
7
4
3
2
1
0
0
will be subject to in the given application. To use the
6
6
=
(AS SELECTED IN FIGURE 17) vs MINIMUM
INPUT VOLTAGE; V
CONFIGURATION; V
(
V
INMAX
7
7
–
V
VCC
8
8
V
18
V
INmin
INmin
) I
⋅
VCC
VCC
BIAS
(V)
(V)
= 5V
9
9
= 5V
BIAS
will dissipate.
10
10
ΔV
ΔV
ΔV
ΔV
ΔV
ΔV
ΔV
ΔV
IN
IN
IN
IN
IN
IN
IN
BIAS
IN
(EQ. 13)
11
11
= 1V
= 2V
= 3V
= 4V
= 5V
= 6V
= 7V
= 8V
ISL6567
power dissipation level of this component. Although Figures
18 through 20 assume a VCC voltage of 5V, the design aid
curves can be translated to a different VCC voltage by
translating them in the amount of the voltage differential, to
the left for a lower VCC voltage, or to the right for a higher
VCC voltage.
Should the simple series bias resistor configuration fall short
of providing the necessary bias current, the internal shunt
regulator can be used in conjunction with an external BJT
transistor to increase the shunt regulator current. Figure 21
details such an implementation utilizing a PNP transistor.
Selection of R
passive regulator configuration. Maximum power dissipation
inside Q
to the circuit and the ISL6567 is disabled; determine
I
the obtained number to calculate Q
An NPN transistor can also be used to increase the
maximum available bias current, as shown in Figure 22.
Used as a series pass element, Q
power when the circuit is enabled and operational, and the
input voltage, V
With the series pass element configuration shown in
Figure 22, the difference between the input and the
regulation level at the VCC pin has to be higher than the
lowest acceptable V
saturation, but must consider the reduced gain). Thus, R
has to be chosen such that it will provide appropriate base
current at lowest V
I
its highest extreme (assume base current goes to 0 when
the IC is disabled). R
added to offset some of the power dissipation in Q
also reduces the available V
series resistor, check that it does not impede on the proper
VREGMAX
VREGMAX
FIGURE 21. INTERNAL SHUNT REGULATOR USE WITH
SHUNT REGULATOR
E/A
1
CIRCUIT
will take place when maximum voltage is applied
POR
+
is not exceeded when the input voltage swings to
by reverse-use of the graph in Figure 18 and use
-
VREF
EXTERNAL PNP TRANSISTOR (ACTIVE
CONFIGURATION)
1
IN
can be based on the graphs provided for the
, is at its highest level.
CE
ISL6567
CE
1
of Q
is an optional circuit element: it can be
of Q
1
. Next, ensure the ISL6567’s
1
CE
(may choose to run Q
VREG
VCC
PVCC
EXTERNAL CIRCUIT
for Q
1
1
will dissipate the most
1
power dissipation.
. If utilizing such a
Q1
R2
(optional)
R1
1
May 28, 2009
1
, but it
into
FN9243.3
V
IN
2