ISL6567CRZ Intersil, ISL6567CRZ Datasheet - Page 20

• Manufacturer Part Number: ISL6567CRZ
• Description: IC CTLR PWM 2PHASE BUCK 24-QFN
• Manufacturer: Intersil

Specifications of ISL6567CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66%
• Voltage - Supply: 4.9 V ~ 5.5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-VQFN
• Frequency-max: 1.5MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

C
poles and zeros of the compensation network:
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
G
G
G
1. Select a value for R
4. Calculate R
2. Calculate C
3. Calculate C2 such that F
3
MOD
FB
CL
) in Figure 23. Use the following guidelines for locating the
value for R
setting the output voltage via an offset resistor connected
to the FB pin, R
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier, in order to compensate for the
attenuation introduced by the resistor divider, the
obtained R
(R
unchanged, as long as the compensated R
used.
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
R3
R
C
C
f ( )
f ( )
2
1
2
P
f ( )
+R
=
=
=
=
=
=
⋅
=
-------------------------------------------- -
d
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
--------------------- -
F
----------- - 1
---------------------------------------------------- - ⋅
s f ( ) R1
G
F
------------------------------------------------------------------------------------------------------------------------ -
(
S
V
MAX
1
SW
SW
LC
1
MOD
d
----------------------------- -
)/R
OSC
R1
⋅
⋅
+
MAX
+
⋅
V
P2
). F
s f ( ) R
2
2
P
1
–
s f ( ) R
3
2
2
OSC
⋅
. The remainder of the calculations remain
f ( ) G
such that F
for desired converter bandwidth (F
value needs be multiplied by a factor of
V
such that F
⋅
⋅
⋅
FB
1
⋅
is placed below F
R1 F
0.5 F
C
SW
IN
C1
⋅
⋅
V
⋅
⋅
(
O
1
) and closed-loop response (G
IN
C
1
⋅
LC
3
⋅
⋅
⋅
2
in Figure 24, the design procedure can
F
1
FB
+
F
represents the per-channel switching
⋅
⋅
LC
⋅
+
CE
s f ( )
C
0
LC
----------------------------------------------------------------------------------------
1
1
C
(to adjust, change the 0.5 factor to
f ( )
C
3
+
(1kΩ to 5kΩ, typically). Calculate
1
)
2
–
s f ( )
Z1
⋅
⋅
P1
Z2
)
1
(
⎛
⎜
⎝
20
R1
1
C3
is placed at a fraction of the F
is placed at F
is placed at F
⋅
+
(
1
+
E
s f ( ) R
=
where s f ( )
+
R3
SW
+
CE
-------------------------------------------------
2π R3 0.7 F
s f ( ) E C
D
⋅
) C3
) C
/F
⋅
(typically, 0.5 to 1.0
⋅
⋅
2
⋅
,
LC
MOD
⋅
⎛
⎜
⎝
+
, the lower the F
⋅
-------------------- -
C
⋅
P2
C
CE
LC
LC
1
s
1
1
2
), feedback
=
+
. Calculate C
f ( ) L C
).
lower in
⋅
.
C
⋅
2
C
2π f j
⋅
2
2
value is
SW
⎞
⎟
⎠
⋅ ⋅
CL
⎞
⎟
⎠
⋅
0
). If
(EQ. 19)
(EQ. 15)
(EQ. 17)
(EQ. 16)
):
(EQ. 18)
LC
Z1
3
ISL6567
,
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 25 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log-log graph of Figure 25 by adding the modulator gain,
G
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain. A stable control loop has a gain
crossing with close to a -20dB/decade slope and a phase
margin greater than 45°. Include worst case component
variations when determining phase margin. The mathematical
model presented makes a number of approximations and is
generally not accurate at frequencies approaching or
exceeding half the switching frequency. When designing
compensation networks, select target crossover frequencies in
the range of 10% to 30% of the per-channel switching
frequency, F
OUTPUT FILTER DESIGN
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the square
wave voltage at the phase nodes. Additionally, the output
capacitors must also provide the energy required by a fast
transient load during the short interval of time required by the
controller and power train to respond. Because it has a low
bandwidth compared to the switching frequency, the output
filter limits the system transient response leaving the output
F
FIGURE 25. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Z2
MOD
F
0
Z1
=
LOG
(in dB), to the feedback compensation gain, G
------------------------------------------------ -
2π
20
=
log
⋅
------------------------------ -
2π R
(
R
SW
⎛
⎝
R2
------- -
R1
⋅
1
1
+
.
1
⎞
⎠
2
R
⋅
3
C
F
) C
1
Z1
⋅
F
F
LC
3
P2
Z2
against the capabilities of the error
F
F
F
CE
P1
P1
F
P2
=
CL
F
0
-------------------------------------------- -
2π R
F
=
, is constructed on the
20
P2
------------------------------ -
2π R
⋅
log
G
CL
2
⋅
COMPENSATION GAIN
d
---------------------------------
OPEN LOOP E/A GAIN
⋅
CLOSED LOOP GAIN
MAX V
G
1
-------------------- -
C
3
V OSC
C
MODULATOR GAIN
MOD
1
⋅
1
FREQUENCY
C
+
⋅
⋅
3
C
C
2
IN
2
May 28, 2009
G
FB
(EQ. 20)
FB
FN9243.3
(in