ISL6567CRZ Intersil, ISL6567CRZ Datasheet - Page 19

• Manufacturer Part Number: ISL6567CRZ
• Description: IC CTLR PWM 2PHASE BUCK 24-QFN
• Manufacturer: Intersil

Specifications of ISL6567CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66%
• Voltage - Supply: 4.9 V ~ 5.5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-VQFN
• Frequency-max: 1.5MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

operation at the lowest input voltage and choose a power
rating corresponding to the highest bias current that the
ISL6567 may require to drive the switching MOSFETs.
FREQUENCY COMPENSATION
The ISL6567 multi-phase converter behaves in a similar
manner to a voltage-mode controller. This section highlights
the design consideration for a voltage-mode controller requiring
external compensation. To address a broad range of
applications, a type-3 feedback network is recommended
(see Figure 23).
Figure 24 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable, with a small
number of adjustments, to the multi-phase ISL6567 circuit. The
output voltage (V
VREF, level. The error amplifier output (COMP pin voltage) is
compared with the oscillator (OSC) modified saw-tooth wave to
provide a pulse-width modulated wave with an amplitude of V
at the PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor E.
SHUNT REGULATOR
FIGURE 22. INTERNAL SHUNT REGULATOR USE WITH
FIGURE 23. COMPENSATION CONFIGURATION FOR ISL6567
E/A
CIRCUIT
R1
POR
+
-
VREF
EXTERNAL NPN TRANSISTOR (ACTIVE
CONFIGURATION)
CIRCUIT
OUT
R2
ISL6567
C2
) is regulated to the reference voltage,
R3
C3
C1
19
VREG
VCC
COMP
PVCC
EXTERNAL CIRCUIT
FB
Q1
V
DIFF
(optional)
ISL6567
(V
R2
R1
OUT
)
V
IN
IN
ISL6567
The modulator transfer function is the small-signal transfer
function of V
gain, given by d
filter, with a double pole break frequency at F
F
individual channel inductance and its DCR divided by 2
(equivalent parallel value of the two output inductors), while C
and E represents the total output capacitance and its
equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6567) and the external R
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
margin (better than 45 °). Phase margin is the difference
between the closed loop phase at F
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R
F
CE
FIGURE 24. VOLTAGE-MODE BUCK CONVERTER
LC
=
. For the purpose of this analysis, L and D represent the
CIRCUIT
PWM
---------------------------
2π
⋅
1
COMP
L C
OUT
0
⋅
; typically 0.1 to 0.3 of F
COMPENSATION DESIGN
HALF-BRIDGE
MAX
OSCILLATOR
/V
V
COMP
OSC
E/A
DRIVE
V
R2
IN
ISL6567
/V
. This function is dominated by a DC
C2
+
-
+
VREF
OSC
-
F
C1
CE
, and shaped by the output
=
FB
PHASE
UGATE
LGATE
VDIFF
RGND
VSEN
----------------------- -
2π C E
EXTERNAL CIRCUIT
0dB
⋅
1
SW
1
, R
R3
Ro
and 180°. The
⋅
V
) and adequate phase
2
IN
R1
, R
1
to R
3
C3
LC
L
, C
and a zero at
3
1
, C
, C
V
D
OUT
(EQ. 14)
May 28, 2009
1
C
2
E
to C
, and
FN9243.3
3