ISL6567CRZ Intersil, ISL6567CRZ Datasheet - Page 21

• Manufacturer Part Number: ISL6567CRZ
• Description: IC CTLR PWM 2PHASE BUCK 24-QFN
• Manufacturer: Intersil

Specifications of ISL6567CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66%
• Voltage - Supply: 4.9 V ~ 5.5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-VQFN
• Frequency-max: 1.5MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

capacitor bank to supply the load current or sink the inductor
currents, all while the current in the output inductors
increases or decreases to meet the load demand.
In high-speed converters, the output capacitor bank is
amongst the costlier (and often the physically largest) parts
of the circuit. Output filter design begins with consideration
of the critical load parameters: maximum size of the load
step, ΔI, the load-current slew rate, di/dt, and the maximum
allowable output voltage deviation under transient loading,
ΔV
capacitance, ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates according to
Equation 21.
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors is also responsible for the
majority of the output-voltage ripple. As the bulk capacitors
sink and source the inductor AC ripple current, a voltage
develops across the bulk-capacitor ESR equal to I
once the output capacitors are selected and a maximum
allowable ripple voltage, V
analysis of the available output voltage budget, Equation 22
can be used to determine a lower limit on the output
inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
ΔV
L
≥
MAX
≈
ESR
(
ESL
. Capacitors are characterized according to their
⋅
(
---------------------------------------------------------------- -
)
V
di
---- -
dt
f
IN
S
+
⋅
–
V
(
MAX
2 V
ESR
IN
⋅
⋅
OUT
V
.
) ΔI
PP MAX
) V
(
⋅
PP(MAX)
OUT
21
)
, is determined from an
PP
. Thus,
(EQ. 21)
(EQ. 22)
ISL6567
load current before the output voltage decreases more than
ΔV
While Equation 23 addresses the leading edge, Equation 24
gives the upper limit on L for cases where the trailing edge of
the current transient causes a greater output voltage
deviation than the leading edge.
Normally, the trailing edge dictates the selection of L, if the
duty cycle is less than 50%. Nevertheless, both inequalities
should be evaluated, and L should be selected based on the
lower of the two results. In all equations in this paragraph, L
is the per-channel inductance and C is the total output bulk
capacitance.
LAYOUT CONSIDERATIONS
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying channel current. During the
turnoff, current stops flowing in the upper MOSFET and is
picked up by the lower MOSFET. Any inductance in the
switched current path generates a large voltage spike during
the switching interval. Careful component selection, tight
layout of the critical components, and short, wide circuit
traces minimize the magnitude of voltage spikes.
There are two sets of critical components in a DC/DC
converter using a ISL6567 controller. The power
components are the most critical because they switch large
amounts of energy. Next are small signal components that
connect to sensitive nodes or supply critical bypassing
current and signal coupling.
Although the ISL6567 allows for external adjustment of the
channel-to-channel current balancing (via the R
resistors), it is desirable to have a symmetrical layout,
preferably with the controller equidistantly located from the
two power trains it controls. Equally important are the gate
drive lines (UGATE, LGATE, PHASE): since they drive the
power train MOSFETs using short, high current pulses, it is
important to size them accordingly and reduce their overall
impedance. Equidistant placement of the controller to the
two power trains also helps keeping these traces equally
long (equal impedances, resulting in similar driving of both
sets of MOSFETs).
L
L
≤
≤
MAX
4 C V
--------------------------------
2.5 C
---------------- -
(
ΔI
⋅
(
⋅
)
. This places an upper limit on inductance.
ΔI
2
⋅
)
⋅
2
OUT
(
ΔV
MAX
⋅
(
ΔV
–
MAX
ΔI ESR
⋅
–
ΔI ESR
⋅
)
⋅
(
V
IN
)
–
V
O
)
ISEN
May 28, 2009
(EQ. 24)
(EQ. 23)
FN9243.3