ISL6567CRZ Intersil, ISL6567CRZ Datasheet - Page 25

IC CTLR PWM 2PHASE BUCK 24-QFN

ISL6567CRZ

Manufacturer Part Number
ISL6567CRZ
Description
IC CTLR PWM 2PHASE BUCK 24-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6567CRZ

Pwm Type
Voltage Mode
Number Of Outputs
1
Frequency - Max
1.5MHz
Duty Cycle
66%
Voltage - Supply
4.9 V ~ 5.5 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
0°C ~ 70°C
Package / Case
24-VQFN
Frequency-max
1.5MHz
Rohs Compliant
YES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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INPUT CAPACITOR SELECTION
The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and
largest RMS current required by the circuit. The capacitor
voltage rating should be at least 1.25 times greater than the
maximum input voltage. The input RMS current required for
a multi-phase converter can be approximated with the aid
of Figure 28. For a more exact calculation of the input RMS
current use Equation 34.
As the input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs, their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs. Figure 28 can be used to determine the
input-capacitor RMS current function of duty cycle,
maximum sustained output current (I
peak-to-peak inductor current (I
sustained load current, I
Use a mix of input bypass capacitors to control the input
voltage ripple. Use ceramic capacitance for the high
frequency decoupling and bulk capacitors to supply the
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
I
IN RMS
FIGURE 28. NORMALIZED INPUT RMS CURRENT vs DUTY
(
0.3
0.2
0.1
0
0
)
=
I
O
CYCLE FOR A 2-PHASE CONVERTER
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
2
0.1
(
D D
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
DUTY CYCLE (V
For information regarding Intersil Corporation and its products, see www.intersil.com
2
O
)
+
.
I
0.2
I
L,PP
L,PP
I
2
25
L PP
I
L,PP
,
= 0.75 x I
= 0.5 x I
L,PP
= 0
----- -
12
D
) to the maximum
0.3
O
O
O
O
/V
), and the ratio of the
IN
)
0.4
(EQ. 34)
0.5
ISL6567
RMS current. Minimize the connection path inductance of
the high frequency decoupling ceramic capacitors (from
drain of upper MOSFET to source of lower MOSFET).
For bulk capacitance, several electrolytic or high-capacity MLC
capacitors may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the
surge-current at power-up.
APPLICATION SYSTEM DC TOLERANCE
Although the ISL6567 features a tight voltage reference, the
overall system DC tolerance can be affected by the
tolerance of the other components employed. The resistive
divider used to set the output voltage will directly influence
the system DC voltage tolerance. Figure 29 details the
absolute worst case tolerance stack-up for 1% and 0.1%
feedback resistors, and assuming the ISL6567 is regulating
at 0.8% above its nominal reference. Other component
tolerance stack-ups may be investigated using the following
equation, where REF
multipliers corresponding to V
TOL
FIGURE 29. WORST CASE SYSTEM DC REGULATION
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
=
1
REF
----------------------------------------------------------------------------------------------- -
REF
R
R
STM
PTM
2
TM
TM
TOLERANCE (V
= 1.01
= 0.99
= 1.008
(
------------------------------------------------------------ -
k 1
3
TM
) R
100
k R
4
, R
STM
PTM
PTM
k = V
REF
5
REF
+
, and R
OUT
R
AT 0.8% ABOVE NOMINAL)
PTM
, R
/V
6
REF
S
, and R
STM
1
7
are the tolerance
[%]
P
R
R
REF
, respectively.
STM
PTM
8
TM
= 1.001
= 0.999
May 28, 2009
= 1.008
(EQ. 35)
9
FN9243.3
10

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