DEMO9S08LC60 Freescale Semiconductor, DEMO9S08LC60 Datasheet - Page 173

• Manufacturer Part Number: DEMO9S08LC60
• Description: BOARD DEMO FOR 9S08LC60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08LC60

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08LC60
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08LC
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.3
Figure 10-3
(ICG) module. This section includes a general description and a feature list.
10.3
The oscillator pins are used to provide an external clock source for the MCU. The oscillator pins are gain
controlled in low-power mode (default). Oscillator amplitudes in low-power mode are limited to
approximately 1 V, peak-to-peak.
10.3.1
If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as either
the external clock input or the input of the oscillator circuit as determined by REFS. If upon the first write
to ICGC1, either the FEI mode or SCM mode is selected, this pin is not used by the ICG.
10.3.2
If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as the
output of the oscillator circuit. If upon the first write to ICGC1, either the FEI mode or SCM mode is
Freescale Semiconductor
External Signal Description
(SEE NOTE 2)
(SEE NOTE 2)
Block Diagram
EXTAL — External Reference Clock / Oscillator Input
XTAL — Oscillator Output
is a top-level diagram that shows the functional organization of the internal clock generation
V
V
DDA
SSA
EXTAL
XTAL
NOTES:
1. See
2. Not all HCS08 microcontrollers have unique supply pins for the ICG. See the device pin assignments.
INTERNAL
REFERENCE
GENERATORS
WITH EXTERNAL REF
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
OSCILLATOR (OSC)
Table 8-1
SELECT
TYP 243 kHz
for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK
IRG
8 MHz
Figure 10-3. ICG Block Diagram
RG
SELECT
REF
ICGERCLK
ICGIRCLK
LOCAL CLOCK FOR OPTIONAL USE WITH BDC
AND CLOCK DETECTOR
FREQUENCY
LOOP (FLL)
LOCKED
LOSS OF LOCK
ICG
DCO
ICGDCLK
Chapter 10 Internal Clock Generator (S08ICGV4)
OUTPUT
SELECT
CLOCK
SELECT
CLOCK
SELECT
CLOCK
FIXED
ICGLCLK
FFE
/R
ICGOUT
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