M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 213

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ICR — IIC Clock Rate
Freescale Semiconductor
The ICR bits are used to prescale the bus clock for bit rate selection. These bits are used to define the
SCL divider and the SDA hold value. The SCL divider multiplied by the value provided by the MULT
register (multiplier factor mul) is used to generate IIC baud rate.
SDA hold time is the delay from the falling edge of the SCL (IIC clock) to the changing of SDA (IIC
data). The ICR is used to determine the SDA hold value.
Table 13-3
values can be used to set IIC baud rate and SDA hold time. For example:
Table 13-3
in an SDA hold value of 9.
If the generated SDA hold value is not acceptable, the MULT bits can be used to change the ICR. This
will result in a different SDA hold value.
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
SDA hold time = bus period (s) * SDA hold value
Bus speed = 8 MHz
MULT is set to 01 (mul = 2)
Desired IIC baud rate = 100 kbps
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
100000 = 8000000/(2*SCL divider)
SCL divider = 40
SDA hold time = bus period (s) * SDA hold value
SDA hold time = 1/8000000 * 9 = 1.125 µs
provides the SCL divider and SDA hold values for corresponding values of the ICR. These
shows that ICR must be set to 0B to provide an SCL divider of 40 and that this will result
MC9S08GB/GT Data Sheet, Rev. 2.3
Inter-Integrated Circuit (IIC) Module
213