M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 254

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Development Support
15.5.3.7 Debug Control Register (DBGC)
This register can be read or written at any time.
DBGEN — Debug Module Enable
ARM — Arm Control
TAG — Tag/Force Select
BRKEN — Break Enable
RWA — R/W Comparison Value for Comparator A
254
Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
Controls whether the debugger is comparing and storing information in the FIFO. A write is used to
set this bit (and the ARMF bit) and completion of a debug run automatically clears it. Any debug run
can be manually stopped by writing 0 to ARM or to DBGEN.
Controls whether break requests to the CPU will be tag or force type requests. If BRKEN = 0, this bit
has no meaning or effect.
Controls whether a trigger event will generate a break request to the CPU. Trigger events can cause
information to be stored in the FIFO without generating a break request to the CPU. For an end trace,
CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger
requirements. For a begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL
does not affect the timing of CPU break requests.
When RWAEN = 1, this bit determines whether a read or a write access qualifies comparator A. When
RWAEN = 0, RWA and the R/W signal do not affect comparator A.
1 = DBG enabled.
0 = DBG disabled.
1 = Debugger armed.
0 = Debugger not armed.
1 = CPU breaks requested as tag type requests.
0 = CPU breaks requested as force type requests.
1 = Triggers cause a break request to the CPU.
0 = CPU break requests not enabled.
1 = Comparator A can only match on a read cycle.
0 = Comparator A can only match on a write cycle.
Reset:
Read:
Write:
DBGEN
Bit 7
0
Figure 15-7. Debug Control Register (DBGC)
MC9S08GB/GT Data Sheet, Rev. 2.3
ARM
6
0
TAG
5
0
BRKEN
4
0
RWA
3
0
RWAEN
2
0
Freescale Semiconductor
RWB
1
0
RWBEN
Bit 0
0