M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 224

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Analog-to-Digital Converter (ATD) Module
conversion to the mode control unit. For V
to set the sampled signal level within itself without relying on the S/H machine to deliver them.
The mode control unit organizes the conversion, specifies the input sample channel, and moves the digital
output data from the SAR register to the result register. The result register consists of a dual-port register.
The SAR register writes data into the register through one port while the module data bus reads data out
of the register through the other port.
14.3.2
The S/H machine accepts analog signals and stores them as capacitor charge on a storage node located in
the SAR machine. Only one sample can be held at a time so the S/H machine and the SAR machine can
not run concurrently even though they are independent machines.
various resistors and capacitors.
When the S/H machine is not sampling, it disables its own internal clocks.The input analog signals are
unipolar. The signals must fall within the potential range of V
required to perform special conversions (i.e., convert V
Proper sampling is dependent on the following factors:
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•
Analog source impedance (the real portion, R
— This is the resistive (or real, in the case of high frequencies) portion of the network driving the
analog input voltage V
Analog source capacitance (C
large enough) may help the analog source network charge the ATD input in the case of high R
ATD input resistance (R
circuit in the path between the external ATD input and the ATD sample and hold circuit. This
resistance varies with temperature, voltage, and process variation but a worst case number is
necessary to compute worst case sample error.
Sample and Hold
V
AIN
+
–
Figure 14-3. Resistor and Capacitor Placement
AIN
AIN
R
AS
.
C
– maximum value 7 kΩ) — This is the internal resistance of the ATD
AS
MC9S08GB/GT Data Sheet, Rev. 2.3
AS
) — This is the filtering capacitance on the analog input, which (if
REFL
INPUT PIN
INPUT PIN
INPUT PIN
INPUT PIN
and V
R
R
R
R
REFH
AIN1
AIN2
AIN3
AINn
AS
.
.
.
REFL
– see
CHANNEL
SELECT 0
CHANNEL
SELECT 1
CHANNEL
SELECT 2
CHANNEL
SELECT n
, the SAR machine uses the reference potentials
and V
SSAD
Appendix A, “Electrical
Figure 14-3
C
REFH
to V
AIN
).
DDAD
ATD SAR
ENGINE
shows the placement of the
. The S/H machine is not
Freescale Semiconductor
Characteristics”)
AS
.