M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 69

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IRQPE — IRQ Pin Enable
IRQF — IRQ Flag
IRQACK — IRQ Acknowledge
IRQIE — IRQ Interrupt Enable
IRQMOD — IRQ Detection Mode
5.8.2
This register includes six read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be
set. Writing any value to this register address clears the COP watchdog timer without affecting the contents
of this register. The reset state of these bits depends on what caused the MCU to reset.
Freescale Semiconductor
This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can be used
as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down
resistor is enabled depending on the state of the IRQMOD bit.
This read-only status bit indicates when an interrupt request event has occurred.
This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF). Writing 0
has no meaning or effect. Reads always return 0. If edge-and-level detection is selected
(IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level.
This read/write control bit determines whether IRQ events generate a hardware interrupt request.
This read/write control bit selects either edge-only detection or edge-and-level detection. The
IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request
events. See
1 = IRQ pin function is enabled.
0 = IRQ pin function is disabled.
1 = IRQ event detected.
0 = No IRQ request.
1 = Hardware interrupt requested whenever IRQF = 1.
0 = Hardware interrupt requests from IRQF disabled (use polling).
1 = IRQ event on falling edges and low levels or on rising edges and high levels.
0 = IRQ event on falling edges or rising edges only.
System Reset Status Register (SRS)
Section 5.5.2.2, “Edge and Level
MC9S08GB/GT Data Sheet, Rev. 2.3
Sensitivity”
Reset, Interrupt, and System Control Registers and Control Bits
for more details.
69