ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet
ZLP128ICE01ZEM
Specifications of ZLP128ICE01ZEM
Related parts for ZLP128ICE01ZEM
ZLP128ICE01ZEM Summary of contents
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... Crimzon Infrared Microcontrollers ZLP12840 OTP MCU with Learning Amplification Product Specification PS024410-0108 ® Copyright ©2008 by Zilog , Inc. All rights reserved. www.zilog.com ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS024410-0108 ...
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Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Revision Date Level January 10 2008 September 09 ...
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Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Transmitting Data Using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . 47 Transmitting Data Using the Interrupt-Driven Method . . . ...
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Crystal 2 Oscillator Pin (XTAL2 ...
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... Architectural Overview Zilog’s ZLP12840 one-time-programmable (OTP) MCU is a member of the Crimzon family of infrared microcontrollers. It provides a directly-compatible code upgrade path to other Crimzon MCUs, offers a robust learning function, and features up to 128 KB OTP read-only memory (ROM) and 1004 bytes of general-purpose random access memory (RAM) ...
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One from LVD • 14 from SMR source P20-P27, P30-P33, P00, P07 – Any change of logic from P20-P27, P30-P33 can generate an interrupt or SMR Additional features include: • IR learning amplifier • Low power consumption—11 mW (typical) ...
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Port 2 pins 0–7 pull-up transistors – EPROM Protection – Watchdog timer enabled at Power-On Reset All signals with an overline, “ ”, are active Low. For example, B/W, in which WORD is Note: active Low, and B/W, in ...
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PS024410-0108 Product Specification 4 Architectural Overview ...
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Pin Description Figure 2 displays the pin configuration of the ZLP12840 device in the 20-pin PDIP, SOIC, and SSOP packages. Figure 2. ZLP12840 MCU 20-Pin PDIP/SOIC/SSOP Pin Configuration Table 3 describes the functions and signal directions of each pin within ...
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Table 3. ZLP12840 MCU 20-Pin PDIP/SOIC/SSOP Sequential Pin Identification (Continued) Pin No Symbol 1 13 P00 P30 14 P01 P20 17 P21 18 P22 19 P23 20 P24 1 When the Port 0 high-nibble pull-up option ...
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Table 4 describes the functions and signal direction of each pin within the 20-pin PDIP, SOIC, and SSOP packages by function. Table 4. ZLP12840 MCU 20-Pin PDIP/SOIC/SSOP Functional Pin Identification Pin No Symbol 1 13 P00 P30 14 P01 4 ...
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Figure 3 displays the pin configuration of the ZLP12840 device in the 28-pin PDIP, SOIC, and SSOP packages. Figure 3. ZLP12840 MCU 28-Pin PDIP/SOIC/SSOP Pin Configuration PS024410-0108 1 P25 28 P24 2 P26 27 P23 3 P27 26 P22 4 ...
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Table 5 describes the functions and signal directions of each pin within the 28-pin PDIP, SOIC, and SSOP packages sequentially by pin. Table 5. ZLP12840 MCU 28-Pin PDIP/SOIC/SSOP Sequential Pin Identification Pin Symbol 1 P25 2 P26 3 P27 4 ...
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Table 6 describes the functions and signal directions of each pin within the 28-pin PDIP, SOIC, and SSOP packages by function. Table 6. ZLP12840 MCU 28-Pin PDIP/SOIC/SSOP Functional Pin Identification Pin Symbol 19 P00 20 P01 21 P02 23 P03 ...
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I/O Port Pin Functions The ZLP12840 MCU features three 8-bit ports, which are described below. • Port 0 is nibble-programmable as either input or output • Port 2 is bit-programmable as either input or output • Port 3 features four ...
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Table 7. I/O Port Control Registers Address (Hex) 12-Bit Bank 8-Bit Register Description Mnemonic 000 0–3 00 002 0–3 02 003 0–3 03 0F6 All F6 0F7 All F7 0F8 All F8 F00 F 00 Port 0 Port 0 is ...
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ZLP12840 OTP MCU Open-Drain I/O Out In Port 2 Port 8-bit, bidirectional, CMOS-compatible I/O port. Its eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O ...
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Open-Drain I/O Out In Port 3 Port 8-bit, CMOS-compatible fixed I/O port. Port 3 consists of four fixed inputs (P33:P30) and four fixed outputs (P37:P34). P30, P31, P32, and P33 are standard CMOS inputs, and can be ...
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P31 (AN1) + – Comp1 P30 (P ) REF1 P31 I REF From Stop-Mode Recovery Source of SMR P31 can be used as an interrupt, analog comparator input, infrared learning amplifier input, normal digital input pin and as a Stop ...
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Register; such reads always return a value of 1. Also, when in ANALOG mode, P31 cannot be used as a Stop Mode Recovery source because in STOP mode, the comparator is disabled, and its output will not toggle. The programming ...
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Table 8. Summary of Port 3 Pin Functions 2 Pin I/O P30 IN P31 IN P32 IN P33 IN P34 OUT P35 OUT P36 OUT P37 OUT Port 3 also provides output for each of the counter/timers and the AND/OR ...
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P31 + – I REF P3M D1 + – P30 Comp1 Figure 7. Port 3 Counter/Timer Output Configuration PS024410-0108 CTR0, bit 0 PCON, bit 0 P34 Data MUX T8_Out MUX P3M D2 IR1 CTR2, bit 0 P35 Data MUX T16_Out ...
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Comparator Inputs In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference is supplied by P33 and P ing IRQ1 are diverted to the Stop Mode Recovery sources (excluding P31, P32, and P33) as displayed in ...
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This register is not reset after a SMR. Note: Port 0 Mode Register The Port 0 Mode Register determines the I/O direction of Port 0. The Port 0 direction is nibble-programmable. Bit 6 controls the upper nibble of Port 0, ...
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Port 0 Register The Port 0 Register allows read and write access to the Port 0 pins Table 11. Port 0 Register (P0) Bit 7 6 P07 P06 Field Reset X X R/W R/W R/W Address Bit Position R/W Description ...
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Port 2 Mode Register The Port 2 Mode Register determines the I/O direction of each bit on Port 2. Bit 0 of the Port 3 Mode Register determines whether the output drive is push/pull or open-drain (Table 12). Table 12. ...
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Port 2 Register The Port 2 Register allows read and write access to the Port 2 pins Table 13. Port 2 Register (P2) Bit 7 6 P27 P26 Field Reset X X R/W R/W R/W Address Bit Position Value Description ...
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Port 3 Mode Register The Port 3 Mode Register is used primarily to configure the functionality of the Port 3 inputs. When bit 2 is set, the IR Learning Amplifier is used instead of the COMP1 comparator, regardless of the ...
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Port 3 Register The Port 3 Register allows read access to port pins P33 through P30 and write access to the port pins P37 through P34 Table 15. Port 3 Register (P3) Bit 7 6 P37 P36 Field Reset 0 ...
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Bit Position Value Description [3] Read Port 3, pin 3 Input—Writing this bit has no effect. If P3M[1]=0: 0 P33 is Low. 1 P33 is High. If P3M[1]=1 or SMR4[4]=1: 0 SMR condition exists. 1 SMR condition does not exist. ...
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Memory and Registers The Z8 LXM CPU used in the ZLP12840 family of devices incorporates special features to extend the available memory space while maintaining the benefits consumer and battery-operated applications. OTP Program/Constant Memory The ZLP12840 family ...
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FFFFh} FFFFh 000Ch (Reset) {0, 0000h} 0000h = 16-bit Address (In Page) {0, 0000h} = {PMPR[0], 16-bit address} (LDC, LDCI Only) Figure 8. Program/Constant Memory Map (128 KB Device) Register File This device features 1056 bytes of register file ...
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F0h–FFh (and the equivalent 4-bit addresses) are bank- independent, meaning they always access the control registers in Bank 0, regardless of the RP[3:0] value. Addresses in the range 00h–03h always access the Bank 0 Port ...
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Banks 1–3 Bank 0 CPU Control CPU Control F0h–FFh General Purpose Registers 04h–EFh Ports 00h–03h Ports 00h–03h = Bank-Independent Address (Always Accesses Bank 0) * Compiler’s default interrupt service routine working registers. Figure 9. Register File 8-Bit Banked Address Map ...
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00: selects Register Bank 0, Working Register Group 0 Register Pointer Example R253 RP = 00h R0 = Port 0 R1 ...
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But if: R253 RP = 0Dh R0 = CTR0 R1 = CTR1 R2 = CTR2 R3 = CTR3 The counter/timers are mapped into ERF group D. Access is easily performed using the following code segment. LD RP, #0Dh LD R0,#xx ...
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As it can be seen in the above example, the source register is referenced via a linear address value contained within registers R6 and R7, whereas the destination is referenced via the SRP setting and a working register. For more ...
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Table 16. Program Memory Paging Register (PMPR) Bit 7 Page Toggle Enable Field 0 Reset R/W R/W Address Bit Position Value Description [7] Page Toggle Enable 0 PMPR[0] changes only when written by software PMPR[0]=0, the CPU toggles ...
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Register Pointer Register The upper nibble of the register pointer of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and, in the case of the ZLP12840 ...
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User Data Register Bank-independent register FEh is available for user data storage Do not use register FEh as a counter for the DJNZ instruction. Note: Table 18. User Data Register (USER) Bit 7 6 Field X X Reset R/W R/W ...
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Table 19. Stack Pointer Register (SPL) Bit 7 6 Field X X Reset R/W R/W R/W Address Bit Position Description [7:0] Stack Pointer PS024410-0108 Stack Pointer R/W R/W R/W Bank Independent: FFh; Linear: 0FFh ...
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PS024410-0108 ZLP12840 OTP MCU Product Specification 38 Memory and Registers ...
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Register File Summary Table 20 maps each linear (12-bit) register file address to the associated register, mne- monic, and reset value. The table also lists the register bank (or banks) and corresponding 8-bit address, if any, for each register, plus ...
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Table 20. Register File Address Summary (Continued) Address (Hex) 12-Bit Bank 8-Bit Register Description 0FB All FB Interrupt Mask Register 0FC All FC Flags Register 0FD All FD Register Pointer 0FE All FE User Data Register 0FF All FF Stack ...
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Table 20. Register File Address Summary (Continued) Address (Hex) 12-Bit Bank 8-Bit Register Description F00 F 00 Port Configuration Register F01–F09 F 01–09 Reserved F0A F 0A Stop Mode Recovery Register 4 F0B F 0B Stop Mode Recovery Register F0C ...
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PS024410-0108 ZLP12840 OTP MCU Product Specification 42 Register File Summary ...
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Infrared Learning Amplifier The ZLP12840 MCU’s infrared learning amplifier allows you to detect and decode infra- red transmissions directly from the output of the receiving diode without the need for external circuitry. See An IR diode can be connected to ...
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PS024410-0108 ZLP12840 OTP MCU Product Specification 44 Infrared Learning Amplifier ...
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Universal Asynchronous Receiver/Transmitter The universal asynchronous receiver/transmitter (UART full-duplex communication channel capable of handling asynchronous data transfers. The two UARTs use a single 8-bit data mode with selectable parity. Features of the UARTs include: • 8-bit asynchronous data ...
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RxD Receive Shifter Receive Data Register System Bus Transmit Data Register Transmit Shift TxD Register Parity Generator Operation The UART channel can be used to communicate with a master microprocessor slave microprocessor, both of which exhibit transmit ...
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Idle state of line lsb 1 Start Bit 0 0 Figure 14. UART Asynchronous Data Format without Parity Idle state of line lsb 1 Start Bit 0 Bit 1 0 Figure 15. UART Asynchronous Data Format with Parity Transmitting Data ...
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To transmit additional bytes, return to 7. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all data in the Transmit Data ...
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Receiving Data Using the Polled Method Follow the steps below to configure the UART for polled data reception: 1. Write to the BCNST register to set the appropriate baud rate. 2. Write to the UART control register (UCTL) to: (a) ...
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Clears the UART receiver interrupt in the applicable Interrupt Request register. 4. Executes the IRET instruction to return from the interrupt service routine and await more data. UART Interrupts The UART features separate interrupts for the transmitter and the ...
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UART Receive Data register is read. The interrupt is cleared by reading the UART Receive Data register. When an overrun error occurs, the additional data byte will not overwrite the data currently stored in the ...
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Figure 16. UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the Baud Rate Generator interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This action allows the Baud Rate Genera- ...
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UART. For programmed register values other than , the UART data rate is calculated using the following equation: 00h UART Data Rate bits/s When the UART Baud Rate Low Register is programmed to calculated ...
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Table 22. BCNST Register Settings Examples (Continued) Target UART Data Rate (baud) 4800 9600 19200 UART Receive Data Register/UART Transmit Data Register The UART Receive/Transmit Data Register is used to send and retrieve data from the UART channel. When the ...
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UART Status Register The UART Status Register shows the status of the UART. Bits [6:3] are cleared by reading the UART Receive/Transmit Register ( Table 24. UART Status Register (UST) Bit 7 6 Receive Parity Field Status Error 0 0 ...
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Bit Position Value Description [0] Read Noise Filter—Detects noise during data reception noise detected. 1 Noise detected. Write 0 Turn OFF noise filter. 1 Turn ON noise filter. UART Control Register As the name implies, the UART Register ...
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Bit Position Value Description [3] 0 Even parity selected. 1 Odd parity selected. [ break is sent. 1 Send Break (force Tx output to 0). [1] 0 One stop bit. 1 Two stop bits. [0] Baud Rate Generator—When ...
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Bit Position Description [7:0] BRG Constant When read, returns the actual timer count value (when UCTL[0]=1). When written, sets the Baud Rate Generator Constant. The actual baud rate frequency = XTAL ÷ (32 x BCNST). PS024410-0108 ...
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Timers ® The Crimzon ZLP12840 MCU infrared timer contains a 16-bit and an 8-bit counter/ timer, each of which can be used simultaneously for transmitting. In addition, both timers can be used for demodulating an input carrier wave. Both timers ...
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Table 27 summarizes the registers used to control timers. Some timer functions can also be affected by control registers for other peripheral functions. Table 27. Timer Control Registers Address (Hex) 12-Bit Bank 8-Bit Register Description D00 D 00 Counter/Timer 8 ...
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The P20 digital signal, if CTR16=1. Based on register bits CTR1[5:4], a pulse is generated at when a rising edge, falling edge, or any edge is detected. Glitches in the input signal are filtered out if they are shorter ...
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Reset T8_ENABLE Bit Load TC8L Reset T8_OUT Set Time-Out Status Bit (CTR0 bit 5) and generate TIMEOUT_INT if enabled Single Pass Load TC8L Reset T8_OUT Figure 19. TRANSMIT Mode Flowchart PS024410-0108 T8 (8-Bit) Transmit Mode No T8_Enable Bit Set CTR0, ...
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When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, bit 1). If the initial value (CTR1, bit TC8L is loaded; otherwise, TC8H is loaded into the counter. In SINGLE-PASS mode (CTR0, Bit 6), ...
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Transition from 0 to Note: Caution: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended. Two successive commands are necessary. First, the counter/timers must be stopped. Sec- ond, the status bits must be ...
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HI8. From that point, one of the edge detect status bits (CTR1, bits [1:0]) is set, and an interrupt can be generated if enabled (CTR0, bit 2). Meanwhile loaded with and starts counting again reaches ...
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This mode is useful for capturing the carrier duty cycle as well as the frequency at which the first cycle is corrupted (see Figure 24 and Figure 25 Disable T8 PS024410-0108 on ...
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Disable T8 Figure 25. DEMODULATION Mode Flowchart with Bit 4 of CTR3 Set PS024410-0108 T8 (8-Bit) Demodulation Mode T8_Enable CTR0 bit 7 No Yes FFh → TC8 Third Edge Present No Yes Enable TC8 T8_Enable Bit Set No Yes No ...
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T16 TRANSMIT Mode In NORMAL or PING-PONG mode, the output of T16 when not enabled, is dependent on CTR1, bit T16_OUT T16_OUT is 0. You can ...
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You can modify the values in TC16H and TC16L at any time. The new values take effect when they are loaded. Caution: Do not load these registers at the time the values are to be loaded into the counter/timer to ...
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Bit 2). T16 is loaded with FFFFh This T16 mode is generally used to measure space time, the length of time between bursts of carrier ...
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Enable TC8 Enable Initiating PING-PONG Mode First, ensure that both counter/timers are not running. Set T8 into SINGLE-PASS mode (CTR0, bit 6), set T16 into SINGLE-PASS mode (CTR2, bit 6), and set the PING-PONG mode (CTR1 bits [3:2]). These instructions ...
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T8_OUT T16_OUT MUX CTR1 data bit 2 CTR1 data bit 3 Counter/Timer Registers Timer 8 Capture High Register The Timer 8 Capture High Register holds the captured data from the output of the 8-bit Counter/Timer 0. Typically, this register contains ...
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Table 28. Timer 8 Capture High Register (HI8) Bit 7 6 Field 0 0 Reset R R R/W Address Bit Position Value Description [7:0] 0hh–FFh T8_Capture_HI—Reads return captured data. Writes have no effect. Timer 8 Capture Low Register The Timer ...
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Table 30. Timer 16 Capture High Register (HI16) Bit 7 6 Field 0 0 Reset R R R/W Address Bit Position Value Description [7:0] 0hh–FFh T16_Capture_HI—Read returns captured data. Writes have no effect. Timer 16 Capture Low Register The Timer ...
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Table 32. Counter/Timer 16 High Hold Register (TC16H) Bit 7 6 Field 0 0 Reset R/W R/W R/W Address Bit Position Value Description [7:0] 0hh–FFh T16_Data_HI—Read/Write Data. Counter/Timer 16 Low Hold Register The Counter/Timer 16 Low Hold Register contains the ...
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Table 34. Counter/Timer 8 High Hold Register (TC8H) Bit 7 6 Field 0 0 Reset R/W R/W R/W Address Bit Position Value Description [7:0] 0hh–FFh T8_Level_HI—Read/Write Data. Counter/Timer 8 Low Hold Register The Counter/Timer 8 Low Hold Register contains the ...
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Ensure to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (DEMODULATION mode) Note: when using the OR or AND commands. These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ...
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Bit Position Value Description [1] Counter_INT_Mask—Disable/enable T8 time-out interrupt. This bit is not reset upon Stop Mode Recovery. 0 Disable time-out interrupt. 1 Enable time-out interrupt. [0] P34_Out—Select normal I output function for Port 3, pin 4. 0 ...
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Table 37. Timer 8 and Timer 16 Common Functions Register (CTR1) Bit 7 6 Mode P36 Out/ Demodulator Field Input 0 0 Reset R/W R/W R/W Address Bit Position Description [7] Mode—Selects the timer mode for signal transmission or demodulation. ...
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Bit Position Description [3:2] TRANSMIT Mode Submode Selection—Select normal or PING-PONG mode operation, or force T16 output. When these bits are written to 00b (NORMAL mode) or 01b (PING-PONG mode), T16_OUT assumes the opposite state of bit CTR1[0] until the ...
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Bit Position Description [0] TRANSMIT Mode Initial Timer 16 Out—In NORMAL or PING-PONG mode, this bit selects the initial T16_OUT state when Timer 16 is enabled. While the timer is disabled, the opposite state is asserted on the pin to ...
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Timer 16 Control Register Table 38 describes the bits for the Timer 16 Control Register (CTR2). Table 38. Counter/Timer 16 Control Register (CTR2) Bit 7 6 Single/ T16_Enable Field Modulo Reset R/W R/W R/W Address Bit Position Description ...
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Bit Position Description [2] Capture_INT_Mask—Disable/enable interrupt when data is captured into either LO16 or HI16 upon a positive or negative edge detection in DEMODULATION mode. This bit is not reset upon Stop Mode Recovery. 0 Disable data capture interrupt. 1 ...
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Bit Position Value Description [5] SYNC Mode—When enabled, the first pulse of Timer 8 (the carrier) is always synchronized with Timer 16 (the demodulated signal). It can always provide a full carrier pulse. This bit is not reset upon Stop ...
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Interrupts ® The Crimzon ZLP12840 MCU features six different interrupts (see The interrupts are maskable and prioritized (see divided as follows: three sources are claimed by Port 3 lines P33:P31, two by the counter/ timers and one for low-voltage detection. ...
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P32 UCTL bits 5 & P31 Interrupt Edge IRQ Register (bits 6 & 7) Select IRQ2 Interrupt Request Figure 31. Interrupt Block Diagram PS024410-0108 UART R P33 Stop-Mode Recovery Source X P3M[1] OR SMR4[ ...
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Table 41. Interrupt Types, Sources, and Vectors Name Source IRQ0 P32, UART Rx IRQ1 P33, UART Tx, BRG, SMR Event IRQ2 P31 IRQ3 Timer 16 IRQ4 Timer 8 IRQ5 Low-Voltage Detection 10,11 When more than one interrupt is pending, priorities ...
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Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and bit 6. The configuration is indicated in Table 42. Interrupt Request Register IRQ Bit Interrupt Edge 7 6 IRQ2 (P31 ...
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Interrupt Priority Register The Interrupt Priority Register priority. Interrupts are divided into three groups of two—Group A, Group B, and Group C. IPR bits 4, 3, and 0 determine which interrupt group has priority. For example, if interrupts IRQ5, IRQ1, ...
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Interrupt Request Register Bits 7 and 6 of the Interrupt Request Register are used to configure the edge detection of the interrupts for Port 3, bit 1 and Port 3, bit 2. The remaining bits, 5 through 0, indicate the ...
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Bit Position Value Description [2] Read IRQ2 (Port 3 Bit 1 Input) 0 Interrupt did not occur. 1 Interrupt occurred. Write 0 Clear interrupt. 1 Set interrupt. [1] Read IRQ1 (Port 3 Bit 3 Input/SMR Event/UART T 0 Interrupt did ...
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Interrupt Mask Register Bits [5:0] are used to enable the interrupt. Bit 7 is the status of the master interrupt. When reset, all interrupts are disabled. When writing bit 7, you must also execute the EI instruction ...
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... However, crystal needs longer startup time than the resonator. The large loading capacitance slows down the oscillation startup time. Zilog suggests not to use more than 10 pF loading capacitor for the crystal. If the stray capacitance of the PCB or the crystal is high, the loading ...
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Stop Mode Recovery delay needs to be selected (bit 5 of SMR = 1). For both resonator and crystal oscillator, the oscillation ground must go directly to the ground pin ...
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Resets and Power Management The ZLP12840 provides the following reduced-power modes, power monitoring, and reset features: • Power-On Reset—Starts the oscillator and internal clock and initializes the system to its power-on reset defaults. • Voltage Brownout Standby—Stops the oscillator and ...
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Table 46. Reset and Power Management Registers (Continued) Address (Hex) 12-Bit Bank 8-Bit Register Description Mnemonic F0C F 0C F0D F 0D F0E F 0E F0F F 0F 5-Clock Filter XTAL Internal RC Oscillator Low Operating Voltage Detection V + ...
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Power-On Reset Timer When power is initially applied to the device, a timer circuit clocked by a dedicated on- board RC-oscillator provides the Power-On Reset timer function. The POR timer circuit is a one-shot timer that keeps the internal reset ...
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The HVD Flag (bit 2 of the LVD register) is set only The LVD Flag (bit 1 of the LVD register) is set only if V HVD. When Voltage Detection is enabled, the LVD Flag ...
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FF 7F Power consumption during HALT mode can be reduced by first setting SMR[0]=1 to enable the divide-by-16 clock prescaler. STOP Mode This instruction turns OFF the internal clock and external crystal oscillation, reducing the MCU supply current to a ...
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Stop Mode Recovery Event Sources Any Port input pin can be configured to generate a SMR event, either individually variety of logical combinations. The PartName provides the following registers for SMR source configuration and ...
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V CC P31 P32 P33 P27 P20 P23 P20 P27 Figure 35. SMR Register-Controlled Event Sources PS024410-0108 SMR[4:2] = 000 SMR[4:2] = 010 SMR[4:2] = 011 The SMR register logic ignores any pin configured as an output in the P2M ...
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Table 48. Stop Mode Recovery Register (SMR) Bit 7 6 Stop Stop Mode Field Flag Recovery Level 0 0 Reset R W R/W Address Bit Position Value Description [7] Stop Flag—Indicates whether last startup was power-on Reset or Stop ...
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SMR1 Register Events The SMR1 register can be used to configure one or more Port 2 pins compared to a written or sampled reference value and generate a SMR event when the pin state dif- fers ...
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Individual Port 2 Pin SMR Logic, Bit P2M[ Bit SMR1[ Port 2, Pin n Bit P2 Port 2 Read/Write P20 Logic P21 Logic P22 Logic P23 Logic P24 Logic P25 Logic P26 Logic P27 Logic Figure 36. SMR1 ...
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Table 49. Stop Mode Recovery Register 1 (SMR1) Bit 7 6 P27 Stop P26 Stop Field Select Select 0 0 Reset W W R/W Address Bit Position Value Description [7] 0 P27 not selected. 1 P27 selected as an SMR ...
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SMR2 Register Events The SMR2 register function is similar to the standard SMR feature used in previous Z8 CPU-compatible parts. Register bits SMR2[4:2] are set to select one of seven event modes, as displayed in the state of SMR2[6]; when ...
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Table 50. Stop Mode Recovery Register 2 (SMR2) Bit 7 Reserved Stop Mode Recovery Field X Reset — R/W Address Bit Position Value Description [7] — Reserved—Read is undefined; write must be 0. [6] Stop Mode Recovery Level 2 Selects ...
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To configure a Port 3 input pin as an SMR3 event source set the corresponding SMR3 reg- ister bit. By default, a SMR event occurs when the pin’s state is zero. After a Port 3 pin is configured as an ...
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Port 3, Pin Port 3 Read/Write Figure 38. SMR3 Register-Controlled Event Sources PS024410-0108 n Individual Port 3 Pin SMR Logic, = 0-3 n Bit SMR3 Bit P3[ ] P3M[1] OR SMR4[4] P30 Logic P31 Logic ...
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Table 51. Stop Mode Recovery Register 3 (SMR3) Bit — Field Reset — — — R/W Address Bit Position Value Description [7:4] — Reserved—Reads undefined; writes have no effect. [3] 0 P33 not selected. ...
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Stop Mode Recovery Register 4 The Stop Mode Recovery Register 4 (SMR4) Register enables the SMR interrupt source and indicates the reference value status for registers SMR1 and SMR3. Table 52. Stop Mode Recovery Register 4 (SMR4) Bit 7 6 ...
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Watchdog Timer The Watchdog Timer is a retriggerable one-shot timer that resets the Z8 LXM CPU if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT instruction, ...
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Bit Position Value Description [1:0] Time-Out Select—Selects the WDT time period minimum minimum minimum minimum. PS024410-0108 ZLP12840 ...
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PS024410-0108 ZLP12840 OTP MCU Product Specification 114 Resets and Power Management ...
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Z8 LXM CPU Programming Summary This chapter provides information for programming the Z8 LXM CPU included in this device. For details on the CPU and its instruction set, refer to Z8 LXM CPU Core User Manual (UM0183). Addressing Notation Table ...
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Table 54. Symbolic Notation for Operands (Continued) Assembly Symbol Operand Description Irr1 @Rn Indirect Working Register Irr2 Ir1 or Ir2 represents the name a working register, Rn, where 2,..., 15. @ indicates Indirect Working Register addressing ...
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Table 55 consists of additional symbols that are used throughout the instruction set summary. Table 55. Additional Symbols Symbol Definition dst Destination Operand src Source Operand @ Indirect Address Prefix C Carry Flag SP Stack Pointer Value PC Program Counter ...
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Flags Register The Flags Register provides information on the current status of the Z8 CPU. It consists of six bits of status information Table 56. Flags Register (FLAGS) Bit Field X X Reset R/W R/W R/W ...
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Bit Position Value Description [1] User Flag 1 (F1) Available to software for use as a general-purpose bit. 0 Bit Clear 1 Bit Set [0] User Flag 2 (F2) Available to software for use as a general-purpose bit. 0 Bit ...
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Table 57. Condition Codes (Continued) Assembly Binary Hex Mnemonic Definition 1011 B UGT 1100 C NOV 1101 D PL 1110 E NZ 1110 E NE 1111 F NC 1111 F UGE Z8 LXM CPU Instruction Summary Table 58 summarizes the ...
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Table 58. Z8 LXM CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation ← ADD dst, src dst dst + src ← AND dst, src dst dst AND src ← CALL dst ← @SP PC ← PC dst ...
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Table 58. Z8 LXM CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation ← DEC dst dst dst – 1 ← DECW dst dst dst – Disable Interrupts IRQCTL[7] ← DJNZ dst, RA dst dst – dst ...
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Table 58. Z8 LXM CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation ← LD dst, src dst src ← LDC dst, src dst src ← LDCI dst, src dst src ← ← ...
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Table 58. Z8 LXM CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation ← POP dst dst @SP ← ← PUSH src SP SP – 1 ← @SP src ← RCF C 0 ← RET PC @SP ...
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Table 58. Z8 LXM CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation ← SRP src RP src STOP STOP Mode ← SUB dst, src dst dst – src dst[7:4] ↔ dst[3:0] SWAP dst TCM dst, src (NOT dst) AND src ...
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Table 58. Z8 LXM CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation ← XOR dst, src dst dst XOR src Flag States State Depends on Result; – Change Undefined Cleared ...
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Electrical Characteristics Absolute Maximum Ratings Stresses greater than those listed in These ratings are stress ratings only. Functional operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to ...
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Standard Test Conditions The characteristics listed in this product specification apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (see Figure 39). Capacitance Table 60 lists the capacitances. Table ...
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DC Characteristics Table 61 describes the direct current characteristics of the ZLP12840 OTP MCU. Table 61. DC Characteristics Symbol Parameter 1 V Supply Voltage CC V Clock Input High CH Voltage V Clock Input Low CL Voltage V Input High ...
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... IR amp current for I DET signal detection Notes ® 1. Zilog recommends adding a filter capacitor (minimum 0.1 voltage fluctuations are anticipated, such as those resulting from driving an infrared LED. 2. All outputs unloaded, inputs at rail. 3. CL1 = CL2 = 100 pF. 4. Oscillator stopped. 5. Oscillator stops when V ...
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AC Characteristics Figure 40 and Table 62 Clock IRQ N 8 Clock Setup Stop-Mode Recovery Source PS024410-0108 on page 132 describe the alternating current (AC) characteristics ...
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Table 62. AC Characteristics Sl No Symbol Parameter Input Clock Period C,T C Clock Input Rise and Fall Times Input Clock Width Timer ...
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Table 62. AC Characteristics (Continued Symbol Parameter 14 f Maximum frequency of MAX input signal for IR amplifier 15 f Minimum frequency of MIN input signal for IR amplifier Notes 1. Timing Reference uses 0 ...
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PS024410-0108 Product Specification 134 Electrical Characteristics ...
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Packaging Figure 41 displays the 28-pin shrink small outline package (SSOP) for the ZLP12840 device DETAIL SEATING PLANE Figure 41. 28-Pin SSOP Package Diagram PS024410-0108 C MILLIMETER SYMBOL MIN ...
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Figure 42 displays the 28-pin small outline integrated circuit (SOIC) package for the ZLP12840 device. Figure 42. 28-Pin SOIC Package Diagram PS024410-0108 ZLP12840 OTP MCU Product Specification 136 Packaging ...
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Figure 43 displays the 28-pin plastic dual inline package (PDIP) for the ZLP12840 device. Figure 43. 28-Pin PDIP Package Diagram PS024410-0108 ZLP12840 OTP MCU Product Specification 137 Packaging ...
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Figure 44 displays the 20-pin shrink small outline package (SSOP) for the ZLP12840 device. Figure 44. 20-Pin SSOP Package Diagram PS024410-0108 ZLP12840 OTP MCU Product Specification 138 Packaging ...
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Figure 45 displays the 20-pin small outline integrated circuit (SOIC) package for the ZLP12840 device. Figure 45. 20-Pin SOIC Package Diagram PS024410-0108 ZLP12840 OTP MCU Product Specification 139 Packaging ...
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Figure 46 displays the 20-pin plastic dual inline package (PDIP) for the ZLP12840 device. Figure 46. 20-Pin PDIP Package Diagram PS024410-0108 ZLP12840 OTP MCU Product Specification 140 Packaging ...
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Ordering Information Table 63 provides a product specification index code and a brief description of each part. Each of the parts listed in The use of lead-free packaging adheres to a socially responsible environmental standard. For a description of a ...
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... Zilog Developer Studio II (ZDSII), available for download at For valuable information about customer and technical support as well as hardware and software development tools, visit the Zilog web site at www.zilog.com. The latest released version of ZDS can be downloaded from this web site. Part Number Description ® ...
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... The document states what Zilog knows about this product at this time, but additional features or nonconformance with some aspects of the document might be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery might be uncertain at times due to start-up yield issues ...
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PS024410-0108 ZLP12840 OTP MCU Product Specification 144 Ordering Information ...
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Index Numerics 12-bit address map 33 16-bit counter/timer circuits 68 20-pin package pins 5, 7 PDIP package 140 SOIC package 139 SSOP package 138 28-pin package pins PDIP package 137 SOIC package 136 SSOP package 135 8-bit ...
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D data format, UART 46, 47 data handling, UART 51 DC characteristics 129 demodulation changing mode 78 flowchart 65, 66 timer 64, 69 demodulation mode flowchart 67 device architecture 1 block diagram 3 features 1 part numbers 141 diagram, package ...
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M map program/constant memory 28 register 12-bit 33 register 8-bit 30 register file summary 39 maximum ratings 127 MCU block diagram 3 features 1 part numbers 141 memory address, linear 32 program/constant 27 program/constant map 28 register 12-bit map 33 ...
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R ratings, maximum 127 register BCNST 57 CTR1 79 CTR3 83 HI16 74 HI8 73 IMR 92 IPR 89 IRQ 88, 90 LO16 74 LO8 73 LVD P01M ...
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T T16_OUT signal modulo-N mode 69 single-pass mode 69 T8_OUT signal modulo-N mode 64 single-pass mode 64 TCLK signal 94 terminal count, reset 76 test conditions 128 test load 128 timer block diagram ...
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W watchdog timer description 112 diagram 96 Watchdog Timer Mode Register (WDTMR) 112 X XTAL1 pin 94 XTAL2 pin 94 Z ZLP12840 MCU block diagram 3 features 1 part numbers 141 PS024410-0108 ...
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... Customer Support For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com. PS024410-0108 ...