ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 51

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ZLP128ICE01ZEM

Manufacturer Part Number
ZLP128ICE01ZEM
Description
EMULATOR CRIMZON Z8 ZLP12840
Manufacturer
Zilog

Specifications of ZLP128ICE01ZEM

Interface Type
RS-232, Ethernet, USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3829
Universal Asynchronous
Receiver/Transmitter
PS024410-0108
Table 21. UART Control Registers
12-Bit
0F1
0F2
0F3
0F4
Architecture
Address (Hex)
Bank 8-Bit
All
All
All
All
The universal asynchronous receiver/transmitter (UART) is a full-duplex communication
channel capable of handling asynchronous data transfers. The two UARTs use a single
8-bit data mode with selectable parity. Features of the UARTs include:
The UARTs consist of three primary functional blocks: transmitter, receiver, and Baud
Rate Generator. The UART transmitter and receiver function independently, but employ
the same baud rate and data format.
F1
F2
F3
F4
8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
One or two Stop bits
Separate transmit and receive interrupts
Framing, overrun, and break detection
Separate transmit and receive enables
8-bit Baud Rate Generator (BRG)
Baud Rate Generator timer mode
UART operational during HALT mode
Register Description
UART Receive/Transmit Data Register
UART Status Register
UART Control Register
UART Baud Rate Generator Constant
P R E L I M I N A R Y
Figure 13
on page 46 displays the UART architecture.
Mnemonic
URDATA/
UTDATA
UST
UCTL
BCNST
Universal Asynchronous Receiver/
Product Specification
ZLP12840 OTP MCU
Reset
XXh
0000_0010b
00h
FFh
Page
No
54
55
56
57
45

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