ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 61

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ZLP128ICE01ZEM

Manufacturer Part Number
ZLP128ICE01ZEM
Description
EMULATOR CRIMZON Z8 ZLP12840
Manufacturer
Zilog

Specifications of ZLP128ICE01ZEM

Interface Type
RS-232, Ethernet, USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3829
Table 24. UART Status Register (UST)
PS024410-0108
Bit
Field
Reset
R/W
Address
Bit
Position
[7]
[6]
[5]
[4]
[3]
[2]
[1]
UART Status Register
Value Description
Receive
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Status
R/W
The UART Status Register shows the status of the UART. Bits [6:3] are cleared by reading
the UART Receive/Transmit Register (
7
0
Receive Status—Set when data is received; cleared when URDATA is read.
UART Receive Data Register empty.
UART Receive Data Register full.
Parity—Set when a parity error occurs; cleared when URDATA is read.
No parity error occurs.
Parity error occurs.
Overrun—Set when an overrun error occurs; cleared when URDATA is read.
No overrun error occurs.
Overrun error occurs.
Framing—Set when a framing error occurs; cleared when URDATA is read.
No framing error occurs.
Framing error occurs.
Break—Set when a break is detected; cleared when URDATA is read.
No break occurs.
Break occurs.
Transmit Data Status—Set when the UART is ready to transmit; cleared when
TRDATA is written.
Do not write to the UART Transmit Data Register.
UART Transmit Data Register ready to receive additional data.
Transmit Completion Status
Data is currently transmitting.
Transmission is complete.
Parity
Error
R/W
6
0
Overrun
Error
R/W
Bank Independent: F2h; Linear: 0F2h
P R E L I M I N A R Y
5
0
Framing
Error
R/W
4
0
F1h
)
(Table
Break
R/W
3
0
24).
Transmit
Data
R/W
Universal Asynchronous Receiver/
2
0
Product Specification
ZLP12840 OTP MCU
Complete
Transmit
R/W
1
1
Noise
Filter
R/W
0
0
55

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