ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 121

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

Z8 LXM CPU Programming Summary
.
Table 54. Symbolic Notation for Operands
PS024410-0108
Symbol
cc
IM
r1
r2
rr1
rr2
R1
R2
RR1
RR2
Addressing Notation
Assembly
Operand
–
#n
Rn
RRn
%
%
aa
aa
This chapter provides information for programming the Z8 LXM CPU included in this
device. For details on the CPU and its instruction set, refer to Z8 LXM CPU Core User
Manual (UM0183).
Table 54
variable n represents a decimal number; aa represents a hexadecimal address; and LABEL
represents a label defined elsewhere in the assembly source.
In reference notation only, lowercase is used to distinguish 4-bit addressed working regis-
ters (r1, r2) from 8-bit addressed registers (R1, R2). The numerals 1 and 2, respectively,
indicate whether the register is used for destination or source addressing.
Description
E0h–EFh (escaped mode), the equivalent 12-bit address is
{RP[3:0], RP[7:4], %
Condition Code
cc represents a condition code mnemonic. See
Immediate Data
IM represents an Immediate Data value, prefixed by # in assembly language. The
immediate value follows the instruction opcode in program memory. n = 0 to 255.
Working Register
r1 or r2 represents the name, R
equivalent 12-bit address is {RP[3:0], RP[7:4], n}.
Working Register Pair
rr1 or rr2 represents the name, R
n = 0, 2, 4,..., 14. The equivalent 12-bit address is {RP[3:0], RP[7:4], n}.
Register
R1 or R2 represents an 8-bit register address. For addresses 00h–DFh or
F0h–FFh, the equivalent 12-bit address is {RP[3:0], %
E0h–EFh (escaped mode), the equivalent 12-bit address is
{RP[3:0], RP[7:4], %
Register Pair (8-bit Address)
RR1 or RR2 represents the 8-bit address of a register pair. For addresses 00h–DFh
or F0h–FFh, the equivalent 12-bit address is {RP[3:0], %
summarizes Z8 LXM CPU addressing modes and symbolic notation. The text
P R E L I M I N A R Y
aa
aa
[3:0]}.
[3:0]}.
n
, of a working register, where n = 0, 1, 2,..., 15. The
n
, of a working register pair, where
Condition Codes
Z8 LXM CPU Programming Summary
aa
}. For addresses
aa
Product Specification
}. For addresses
ZLP12840 OTP MCU
on page 119.
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