ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 56

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

PS024410-0108
Note:
UART Interrupts
3. Clears the UART receiver interrupt in the applicable Interrupt Request register.
4. Executes the IRET instruction to return from the interrupt service routine and await
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also
function as a basic timer with interrupt capability.
When the UART is set to run at higher baud rates, the UART receiver’s service routine
might not have enough time to read and manipulate all bits in the UART Status register
(especially bits generating error conditions) for a received byte before the next byte is
received. Devise your own hand-shaking protocol to prevent the transmitter from transmit-
ting more data while current data is being serviced.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Status bit, UST[2], is set
to 1. This indicates that the transmitter is ready to accept new data for transmission. The
Transmit Status interrupt occurs after the internal transmit shift register has shifted the first
bit of data out. At this point, the Transmit Data register can be written with the next
character to send. This provides 7 bit periods of latency to load the Transmit Data register
before the transmit shift register completes shifting the current character. Writing to the
UART Transmit Data register clears the UST[2] bit to 0. The interrupt is cleared by
writing a 0 to the Transmit Data register.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
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more data.
A data byte has been received and is available in the UART Receive Data
register—This interrupt can be disabled independent of the other receiver interrupt
sources. The received data interrupt occurs once the receive character has been
received and placed in the Receive Data register. Software must respond to this
received data available condition before the next character is completely received to
avoid an overrun error. The interrupt is cleared by reading from the UART Receive
Data register.
A break is received—A break is detected when a 0 is sent to the receiver for the full
byte plus the parity and stop bits. After a break is detected, it will interrupt
immediately if there is no valid data in the Receive Data register. If data is present in
the Receive Data register, an interrupt will occur after the UART Receive Data
register is read.
An overrun is detected—An overrun occurs when a byte of data is received while
there is valid data in the UART Receive Data register that is not read. The interrupt
P R E L I M I N A R Y
Universal Asynchronous Receiver/
Product Specification
ZLP12840 OTP MCU
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