ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 113

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

Table 50. Stop Mode Recovery Register 2 (SMR2)
PS024410-0108
Bit
Field
Reset
R/W
Address
Bit
Position
[7]
[6]
[5]
[4:2]
[1:0]
Note:
SMR3 Register Events
Value Description
000
001
010
100
101
011
110
111
—
—
—
Reserved
0
1
This register is not reset after a SMR.
The SMR3 register can be used to configure one or more of Port 3, pins 0–3 to be
compared to a written or sampled reference value and generate a SMR event when the pin
state differs from the reference value.
—
X
7
Reserved—Read is undefined; write must be 0.
Stop Mode Recovery Level 2
Selects whether an SMR2[4:2]-selected SMR is initiated by a Low or High level at the
XOR-gate input (see
Low.
High.
Reserved—Read is undefined; write must be 0.
Stop Mode Recovery Source
Specifies a SMR wake-up source at the XOR gate input (see
Additional sources can be selected by SMR, SMR1, and SMR3 registers. If more than
one source is selected, any selected source event causes a SMR. The following
equations ignore any Port pin that is selected in register SMR1 or configured as an
output.
No SMR2 register source selected.
NAND of P23:P20.
NAND of P27:P20.
NOR of P33:P31.
NAND of P33:P31.
NOR of P33:P31, P00, P07.
NAND of P33:P31, P00, P07.
NAND of P33:P31, P22:P20.
Reserved—Read is undefined; write must be 00b.
Stop Mode Recovery
Level 2
W
6
0
P R E L I M I N A R Y
Figure 37
Bank F: 0Dh; Linear: F0Dh
Reserved
on page 106).
—
X
5
W
4
Stop Mode Recovery
0
Source
W
3
0
Resets and Power Management
Figure 37
Product Specification
ZLP12840 OTP MCU
W
2
0
on page 106).
Reserved
X
1
—
X
0
107