ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 39

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

PS024410-0108
Ports 000h–003h
Typical Stack
CPU Control
Below 0D0h
0F0h–0FFh
004h–0EFh
Program Memory Paging Register
Note:
Registers
Purpose
Bank 0
General
As it can be seen in the above example, the source register is referenced via a linear
address value contained within registers R6 and R7, whereas the destination is referenced
via the SRP setting and a working register. For more information on the use of the LDX
and LDXI instructions, refer to Z8 LXM CPU Core User Manual (UM0183).
The LDE and LDEI instructions that existed in the Z8
replaced by the LDX and LDXI instructions.
Bit 0 of the Program Memory Paging Register determines which 64 KB bank of program
memory is read during the execution of the LDC and LDCI instructions
Figure 11. Register File LDX, LDXI Linear 12-Bit Address Map
Banks 1–3
General Purpose
100h–3FFh
Registers
P R E L I M I N A R Y
D10h–DFFh
D00h–D0Fh
Reserved
Peripheral
Bank D
Control
®
CPU are no longer valid; they are
Product Specification
ZLP12840 OTP MCU
Memory and Registers
F10h–FFFh
F00h–F0Fh
(Table
Reserved
Peripheral
Bank F
Not to Scale
Control
16).
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