ATMEGA48A-PU Atmel, ATMEGA48A-PU Datasheet - Page 265
Manufacturer Part Number
IC MCU AVR 4K FLASH 28PDIP
Specifications of ATMEGA48A-PU
I²C, SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
Program Memory Size
4KB (2K x 16)
Program Memory Type
256 x 8
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
No. Of I/o's
Eeprom Memory Size
Ram Memory Size
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-
version on a positive edge of the selected trigger signal. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-
Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI
instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
• Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock
to the ADC.
ADC Prescaler Selections