ATMEGA48A-PU Atmel, ATMEGA48A-PU Datasheet - Page 324

IC MCU AVR 4K FLASH 28PDIP

ATMEGA48A-PU

Manufacturer Part Number
ATMEGA48A-PU
Description
IC MCU AVR 4K FLASH 28PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48A-PU
Manufacturer:
Microchip Technology
Quantity:
1 051
28.6
8271C–AVR–08/10
SPI Timing Characteristics
See
Table 28-14. SPI Timing Parameters
Note:
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 28-3
Description
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
1. In SPI Programming mode the minimum SCK high/low period is:
2. All DC Characteristics contained in this datasheet are based on simulation and characteriza-
- 2 t
- 3 t
tion of other AVR microcontrollers manufactured in the same process technology. These
values are preliminary values representing design targets, and will be updated after character-
ization of actual silicon.
CLCL
CLCL
and
for f
for f
(1)
Figure 28-4
CK
CK
< 12 MHz
> 12 MHz
Mode
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
for details.
Min.
4 • t
2 • t
10
t
20
20
ck
ck
ck
Typ
See
50% duty cycle
3.6
10
10
0.5 • t
10
10
15
15
10
Table 18-5
sck
Max
1600
324
ns

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