PIC24HJ64GP502-E/MM Microchip Technology, PIC24HJ64GP502-E/MM Datasheet - Page 130

• Manufacturer Part Number: PIC24HJ64GP502-E/MM
• Description: IC PIC MCU FLASH 64K 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP502-E/MM

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-QFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit or 10-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.2.2
The following occur in Idle mode:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
• If the WDT or FSCM is enabled, the LPRC also
The device wakes from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (2 to 4
cycles later), starting with the instruction following the
PWRSAV instruction, or the first instruction in the ISR.
10.2.3
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
10.3
The
consumption are changing clock speed and invoking
one
circumstances, this cannot be practical. For example, it
may be necessary for an application to maintain
uninterrupted synchronous communication, even while
it is doing nothing else. Reducing system clock speed
can introduce communication errors, while using a
power-saving
completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70293D-page 130
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Peripheral Module Disable”).
remains active.
of
preferred
Doze Mode
the
IDLE MODE
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
mode
power-saving
strategies
can
stop
for
modes.
reducing
communications
In
power
some
Preliminary
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>).
configurations, from 1:1 to 1:128, with 1:1 being the
default setting.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU idles, waiting for something to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
For example, suppose the device is operating at
20 MIPS and the ECAN module has been configured
for 500 kbps based on this device operating speed. If
the device is placed in Doze mode with a clock
frequency ratio of 1:4, the ECAN module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
10.4
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not have effect and read
values are invalid.
A peripheral module is enabled only if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific PIC MCU
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
Note:
Peripheral Module Disable
If a PMD bit is set, the corresponding
module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control regis-
ters are already configured to enable mod-
ule operation).
There
© 2009 Microchip Technology Inc.
are
eight
possible