PIC24HJ64GP502-E/MM Microchip Technology, PIC24HJ64GP502-E/MM Datasheet - Page 351

• Manufacturer Part Number: PIC24HJ64GP502-E/MM
• Description: IC PIC MCU FLASH 64K 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP502-E/MM

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-QFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit or 10-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Peripheral Module Disable (PMD) .................................... 130
PICkit 2 Development Programmer/Debugger and PICkit 2
PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug
Pinout I/O Descriptions (table) ............................................ 13
PMD Module
PORTA
PORTB
Power-on Reset (POR) ....................................................... 64
Power-Saving Features .................................................... 129
Program Address Space ..................................................... 25
Program Memory
R
Reader Response ............................................................. 354
Register Map
Registers
© 2009 Microchip Technology Inc.
Debug Express ......................................................... 282
Express ..................................................................... 281
Register Map............................................................... 46
Register Map......................................................... 44, 45
Register Map............................................................... 45
Clock Frequency and Switching................................ 129
Construction................................................................ 49
Data Access from Program Memory Using Program
Data Access from Program Memory Using Table Instruc-
Data Access from, Address Generation...................... 50
Memory Map ............................................................... 25
Table Read Instructions
Visibility Operation ...................................................... 52
Interrupt Vector ........................................................... 26
Organization................................................................ 26
Reset Vector ............................................................... 26
CRC ............................................................................ 44
Dual Comparator......................................................... 44
Parallel Master/Slave Port .......................................... 43
Real-Time Clock and Calendar................................... 44
AD1CHS0 (ADC1 Input Channel 0 Select ................ 231
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 230
AD1CON1 (ADC1 Control 1) .................................... 225
AD1CON2 (ADC1 Control 2) .................................... 227
AD1CON3 (ADC1 Control 3) .................................... 228
AD1CON4 (ADC1 Control 4) .................................... 229
AD1CSSL (ADC1 Input Scan Select Low)................ 232
AD1PCFGL (ADC1 Port Configuration Low) ............ 232
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 207
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 208
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 208
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 209
CiCFG1 (ECAN Baud Rate Configuration 1) ............ 205
CiCFG2 (ECAN Baud Rate Configuration 2) ............ 206
CiCTRL1 (ECAN Control 1) ...................................... 198
CiCTRL2 (ECAN Control 2) ...................................... 199
CiEC (ECAN Transmit/Receive Error Count)............ 205
CiFCTRL (ECAN FIFO Control)................................ 201
CiFEN1 (ECAN Acceptance Filter Enable) ............... 207
CiFIFO (ECAN FIFO Status)..................................... 202
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)..... 211,
CiINTE (ECAN Interrupt Enable) .............................. 204
CiINTF (ECAN Interrupt Flag)................................... 203
CiRXFnEID (ECAN Acceptance Filter n Extended Identi-
CiRXFnSID (ECAN Acceptance Filter n Standard Identi-
Space Visibility.................................................... 52
tions .................................................................... 51
TBLRDH ............................................................. 51
TBLRDL .............................................................. 51
212
fier).................................................................... 211
Preliminary
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 214
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 214
CiRXMnEID (ECAN Acceptance Filter Mask n Extended
CiRXMnSID (ECAN Acceptance Filter Mask n Standard
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 215
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 215
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 217,
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 216
CiVEC (ECAN Interrupt Code) ................................. 200
CLKDIV (Clock Divisor) ............................................ 125
CORCON (Core Control)...................................... 23, 73
DMACS0 (DMA Controller Status 0) ........................ 114
DMACS1 (DMA Controller Status 1) ........................ 116
DMAxCNT (DMA Channel x Transfer Count)........... 113
DMAxCON (DMA Channel x Control)....................... 110
DMAxPAD (DMA Channel x Peripheral Address) .... 113
DMAxREQ (DMA Channel x IRQ Select) ................. 111
DMAxSTA (DMA Channel x RAM Start Address A) . 112
DMAxSTB (DMA Channel x RAM Start Address B) . 112
DSADR (Most Recent DMA RAM Address) ............. 117
I2CxCON (I2Cx Control)........................................... 183
I2CxMSK (I2Cx Slave Mode Address Mask)............ 187
I2CxSTAT (I2Cx Status) ........................................... 185
IFS0 (Interrupt Flag Status 0) ............................... 76, 83
IFS1 (Interrupt Flag Status 1) ............................... 78, 85
IFS2 (Interrupt Flag Status 2) ............................... 80, 87
IFS3 (Interrupt Flag Status 3) ............................... 81, 88
IFS4 (Interrupt Flag Status 4) ............................... 82, 89
INTCON1 (Interrupt Control 1) ................................... 74
INTCON2 (Interrupt Control 2) ................................... 75
INTTREG Interrupt Control and Status Register ...... 104
IPC0 (Interrupt Priority Control 0) ............................... 90
IPC1 (Interrupt Priority Control 1) ............................... 91
IPC11 (Interrupt Priority Control 11) ......................... 100
IPC15 (Interrupt Priority Control 15) ......................... 101
IPC16 (Interrupt Priority Control 16) ......................... 102
IPC17 (Interrupt Priority Control 17) ......................... 103
IPC2 (Interrupt Priority Control 2) ............................... 92
IPC3 (Interrupt Priority Control 3) ............................... 93
IPC4 (Interrupt Priority Control 4) ............................... 94
IPC5 (Interrupt Priority Control 5) ............................... 95
IPC6 (Interrupt Priority Control 6) ............................... 96
IPC7 (Interrupt Priority Control 7) ............................... 97
IPC8 (Interrupt Priority Control 8) ............................... 98
IPC9 (Interrupt Priority Control 9) ............................... 99
NVMCON (Flash Memory Control)............................. 55
NVMKEY (Nonvolatile Memory Key) .......................... 56
OCxCON (Output Compare x Control) ..................... 173
OSCCON (Oscillator Control)................................... 123
OSCTUN (FRC Oscillator Tuning)............................ 127
PLLFBD (PLL Feedback Divisor) ............................. 126
PMD1 (Peripheral Module Disable Control Register 1) ..
PMD2 (Peripheral Module Disable Control Register 2) ..
PMD3 (Peripheral Module Disable Control Register 3) ..
RCON (Reset Control)................................................ 60
SPIxCON1 (SPIx Control 1) ..................................... 177
SPIxCON2 (SPIx Control 2) ..................................... 179
SPIxSTAT (SPIx Status and Control) ....................... 176
SR (CPU Status) .................................................. 22, 72
T1CON (Timer1 Control) .......................................... 162
fier) ................................................................... 210
Identifier) .......................................................... 213
Identifier) .......................................................... 213
218, 220
131
132
133
DS70293D-page 351