AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 40

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.16 Triple Data Encryption Standard
10.17 Analog-to-Digital Converter
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AT91SAM7XC512/256/128 Preliminary
• 8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode
• Last Output Data Mode allowing Message Authentication Code (MAC) generation
• Hardware Countermeasures against Differential Power Analysis attacks
• Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes:
• Single Data Encryption Standard (DES) and Triple Data Encryption
• Algorithm (TDEA or TDES) supports
• Compliant with FIPS Publication 46-3, Data Encryption Standard (DES)
• 64-bit Cryptographic Key
• Two-key or Three-key Algorithms
• 18-clock Cycles Encryption/Decryption Processing Time for DES
• 50-clock Cycles Encryption/Decryption Processing Time for TDES
• Support the Four Standard Modes of Operation specified in the FIPS Publication 81, DES
• Modes of Operation:
• 8-, 16-, 32- and 64- Data Sizes Possible in CFB Mode
• Last Output Data Mode allowing Optimized Message (Data) Authentication Code (MAC)
• Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes:
• 8-channel ADC
• 10-bit 384 Ksamples/sec. Successive Approximation Register ADC
• ±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity
• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
• External voltage reference for better accuracy on low voltage inputs
• Individual enable and disable of each channel
• Multiple trigger sources
• Sleep Mode and conversion sequencer
generation
– Counter (CTR)
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
– Electronic Codebook (ECB)
– Cipher Block Chaining (CBC)
– Cipher Feedback (CFB)
– Output Feedback (OFB)
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
6209F–ATARM–17-Feb-09