AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 507

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

36. Advanced Encryption Standard (AES)
36.1
36.2
36.2.1
36.2.2
36.3
6209F–ATARM–17-Feb-09
Description
Product Dependencies
Functional Description
Power Management
Interrupt
The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Infor-
mation Processing Standard) Publication 197 specification.
The AES supports all five confidentiality modes of operation for symmetrical key block cipher
algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 800-
38A Recommendation. It is compatible with all these modes via Peripheral DMA Controller chan-
nels, minimizing processor intervention for large buffer transfers.
The 128-bit input data and initialization vector (for some modes) are each stored in four 32-bit
registers (AES_IDATAxR and AES_IVxR) which are all write-only.
As soon as the initialization vector, the input data and the key are configured, the encryp-
tion/decryption process may be started. Then the encrypted/decrypted data is ready to be read
out on the four 32-bit output data registers (AES_ODATAxR) or through the PDC channels.
The AES may be clocked through the Power Management Controller (PMC), so the programmer
must first to configure the PMC to enable the AES clock.
The AES interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling the AES interrupt requires programming the AIC before configuring the AES.
The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm
that can be used to protect electronic data. The AES algorithm is a symmetric block cipher that
can encrypt (encipher) and decrypt (decipher) information.
Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext
converts the data back into its original form, called plaintext. The CIPHER bit in the AES Mode
Register (AES_MR) allows selection between the encryption and the decryption processes.
The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt data
in blocks of 128 bits. This 128-bit/192-bit/256-bit key is defined in the Key Registers
(AES_KEYWxR).
The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to
the plaintext, a 128-bit data block called the initialization vector (IV), which must be set in the Ini-
tialization Vector Registers (AES_IVxR). The initialization vector is used in an initial step in the
encryption of a message and in the corresponding decryption of the message. The Initialization
Vector Registers are also used by the CTR mode to set the counter value.
• For the AT91SAM7XC256 and AT91SAM7XC128, the 128-bit key is stored in four 32-bit
• For the AT91SAM7XC512, the 128-bit/192-bit/256-bit keys are stored in four/six/eight 32-bit
registers (AES_KEYWxR) which are all write-only.
registers (AES_KEYWxR), respectively, which are all write-only.
AT91SAM7XC512/256/128 Preliminary
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