AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 712

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

712
Version
6209E
(Continued) Comments
AT91SAM7XC512/256/128 Preliminary
USART,
“CLKO: Clock Output Select” on page
“USCLKS: Clock Selection” on page
Section 31.5.1 ”I/O
“TXEMPTY: Transmitter Empty” on page
Section 31.6.2 ”Receiver and Transmitter
RSTTX in US_CR register) updated by replacing 2nd sentence.
Section 31.6.5 ”IrDA
Section 31.2 ”Block
Electrical Characteristics,
Section 40.7 ”ADC
“Transfer
Table 40.3.2, “Peripheral Power Consumption in Active Mode”
Table 40-9, “Main Oscillator
Table 40-11, “XIN Clock Electrical Characteristics”
Figure 40-2, ”XIN CLock Timing” on page
Table 40-6, “Power Consumption for Different
assigned to Ultra Low Power mode.
Table 40-2, “DC
Table 40-2, “DC
Table 40-16, “External Voltage Reference
Section 41.1 “Thermal Considerations”, removed.
Table 41-3, “Package
Table 40-25, “Embedded Flash Wait States (AT91SAM7XC256/128)”
States (AT91SAM7XC512)”
Errata,
Section 44.2 ”AT91SAM7XC256/128 Errata - Rev. A Parts”
Section 44.2.2 ”Controller Area Network
Section 44.2.10.1 ”USART: CTS in Hardware
Section 44.2.10.3 ”USART: RXBRK Flag Error in Asynchronous
Section 44.2.10.4 ”USART: DCD is Active High instead of
Section 44.2.7.6 ”SPI: Bad Serial Clock Generation on 2nd Chip Select”
Section 44.2.1 ”Analog-to-Digital Converter
USART: XOFF Character Bad Behavior, removed
Section 44.3 ”AT91SAM7XC512 Errata - Rev. A Parts”
Section 44.3.2 ”Controller Area Network
Section 44.3.3 ”Embedded FLash Controller
Section 44.3.11.1 ”USART: CTS in Hardware Handshaking”
Section 44.3.11.3 ”USART: RXBRK Flag Error in Asynchronous
Section 44.3.11.4 ”USART: DCD is Active High instead of
Section 44.3.8.6 ”SPI: Bad Serial Clock Generation on 2nd Chip
Section 44.3.8.7 ”SPI: Software Reset must be Written
Section 44.3.1 ”Analog-to-Digital Converter
USART: XOFF Character Bad Behavior, removed
Characteristics”, reference to Data Converter Terminology added below table.
Characteristics”, CMOS conditions added to I
Characteristics”, removed reference to Tj.
Lines”, 2nd and 3rd paragraphsupdated.
Characteristics”, INL and DN updated and Absolute accuracy added to
Diagram”, signal directions from pads to PIO updted in the block diagram.
Mode”, updated with instruction to receive IrDA signals.
Reference”, JESD97 Classification is e3
Characteristics”, added schematic in footnote to C
The prododuct specific embedded Flash Wait States are defined.
375, bit field in US_MR register, DIV= 8 in Selected Clock column.
377, bit field in US_MR register, typo fixed in bit field description.
(CAN)”, added
(CAN)”, added.
382, no characters when at 1 updated.
Control”, In the fourth paragraph, Software reset effects (RSTRX and
662, added figure.
Input”, added ADVREF input w/conditions “8-bit resolution mode”.
(ADC)”, added.
(ADC)”,added
(EFC)”,
Handshaking”, updated.
Modes”; Footnote assigned to Flash In standby mode. Footnote
,added t
”EFC: Embedded Flash Access Time”
Twice”, added
Low.”,added
Low.”, added
CLCH
updated.
O
AES and TDES added to
for V
and t
Mode”,added
Mode”, added
Select”, added
OL
CHCL
and
and V
Table 40-26, “Embedded Flash Wait
to table, t
OH
L
.
and C
CHXIN
LEXT
Table 40-18
and t
Table 40-18,
symbols.
added.
CLXIN
updated.
6209F–ATARM–17-Feb-09
Change
Request
Ref.
3306
3763
3851/4825
3895
4367
4912
4905
4008
3485
3869
3968
4597/4599
rfo
4661
rfo
4970
5363
4649
3957
4644
4753
5339
4649
5990
3957
4644
4753
5787
5339