AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 541

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

37.4.6
Name:
Access Type: Read-only
• DATRDY: Data Ready
0 = Output data is not valid.
1 = Encryption or decryption process is completed.
DATRDY is cleared when a Manual encryption/decryption occurs (START bit in TDES_CR) or when a software triggered
hardware reset of the TDES interface is performed (SWRST bit in TDES_CR).
LOD = 0 (TDES_MR):
In Manual and Auto mode, the DATRDY flag can also be cleared when at least one of the Output Data Registers is read.
In PDC mode, DATRDY is set and cleared automatically.
LOD = 1 (TDES_MR):
In Manual and Auto mode, the DATRDY flag can also be cleared when at least one of the Input Data Registers is written.
In PDC mode, DATRDY is set and cleared automatically.
• ENDRX: End of RX Buffer
0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR.
Note:
• ENDTX: End of TX Buffer
0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR.
Note:
• RXBUFF: RX Buffer Full
0 = TDES_RCR or TDES_RNCR has a value other than 0.
Note:
Both TDES_RCR and TDES_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty
0 = TDES_TCR or TDES_TNCR has a value other than 0.
6209F–ATARM–17-Feb-09
31
23
15
–
–
7
–
This flag must be used only in PDC mode with LOD bit cleared.
This flag must be used only in PDC mode with LOD bit set.
1 =
TDES Interrupt Status Register
This flag must be used only in PDC mode with LOD bit cleared.
TDES_ISR
30
22
14
–
–
6
–
29
21
13
–
–
5
–
URAT
AT91SAM7XC512/256/128 Preliminary
TXBUFE
28
20
12
–
–
4
RXBUFF
27
19
11
–
–
–
3
ENDTX
26
18
10
–
–
–
2
ENDRX
25
17
–
–
–
9
1
DATRDY
URAD
24
16
–
–
8
0
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